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hcs08 microcontrollers freescale.com mc9s08el32 mc9s08el16 mc9s08sl16 mc9s08sl8 data sheet mc9s08el32 rev. 3 7/2008

8-bit hcs08 central processor unit (cpu) ? 40-mhz hcs08 cpu (central processor unit) ? hc08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources on-chip memory ? flash read/program/erase over full operating voltage and temperature ? eeprom in-circuit pr ogrammable memory; program and erase while executing flash; erase abort ? random-access memory (ram) ? security circuitry to prevent unauthorized access to ram and nvm contents power-saving modes ? two very low-power stop modes ? reduced power wait mode ? very low-power real-time interrupt for use in run, wait, and stop clock source options ? oscillator (xosc) ? loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz ? internal clock source (ics) ? contains a frequency-locked loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 2?20 mhz system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1-khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode detection with reset ? illegal address detection with reset ? flash and eeprom block protect development support ? single-wire background debug interface ? breakpoint capability allo ws single breakpoint setting during in-circuit debugging (plus two more breakpoints in the on-chip debug module) ? in-circuit emulation (ice) debug module ? contains two comparators and nine trigger modes; eight-deep fifo for storing change-of-flow address and event-only data; supports both tag and force breakpoints peripherals ? adc ? 16-channel, 10-bit resolution, 2.5 s conversion time, automatic compare function, temperature sensor, internal bandgap reference channel; runs in stop3 ? acmpx ? two analog comparators with selectable interrupt on ri sing, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; output can optionally be routed to tpm module; runs in stop3 ? sci ? full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake-up on active edge ? slic ? supports lin 2.0 and sae j2602 protocols; up to 120 kbps, full lin message buffering, automatic bit rate and frame synchronization, checksum generation and verification, uart-like byte transfer mode ? spi ? full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting ? iic ? up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer ? tpmx ? one 4-channel (tpm1) and one 2-channel (tpm2); selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel ? rtc ? 8-bit modulus real-time counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar, or task scheduling functions; free running on-chip low powe r oscillator (1 khz) for cyclic wake-up without external components input/output ? 22 general purpose i/o pins ? 16 interrupt pins wit h selectable polarity ? hysteresis and configurable pull up device on all input pins; configurable slew rate and drive strength on all output pins. package options ?28-tssop ?20-tssop mc9s08el32 features

mc9s08el32 data sheet covers mc9s08el32 mc9s08el16 mc9s08sl16 mc9s08sl8 mc9s08el32 rev. 3 7/2008 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2008. all rights reserved.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 6 freescale semiconductor revision history to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summ arizes changes contained in this document. revision number revision date description of changes 3 07/2008 initial public revision ? freescale semiconductor, inc., 2008. all rights reserved. this product incorporates superflash ? technology licensed from sst.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 7 list of chapters chapter 1 device overview ..... .................................... ............................. 19 chapter 2 pins and connection s ................................ ............................. 25 chapter 3 modes of operatio n .................................... ............................. 31 chapter 4 memory .......................... .................................... ....................... 37 chapter 5 resets, interrupts, and general system control.................. 63 chapter 6 parallel input/output control............... ................................... 79 chapter 7 central processor unit (s08cpuv3) ... ................................... 95 chapter 8 internal clock source (s08icsv2)............. ........................... 115 chapter 9 5-v analog comparator (s08acmpv2)..... ........................... 129 chapter 10 analog-to-digital conv erter (s08adcv1) ............................ 137 chapter 11 inter-integrated circui t (s08iicv2) ............ ........................... 165 chapter 12 slave lin interface cont roller (s08slicv1 ) ........................ 185 chapter 13 serial peripheral inte rface (s08spiv3) ................................ 233 chapter 14 serial communications in terface (s08sciv 4)..................... 249 chapter 15 real-time counter (s 08rtcv1) ................ ........................... 269 chapter 16 timer pulse-width modulator (s08tpmv2) ......................... 279 chapter 17 development support . ......................... ........................ ......... 307 appendix a electrical characteri stics...................................................... 331 appendix b ordering information and mechanical draw ings................ 355
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 8 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 9 contents section number title page chapter 1 device overview 1.1 devices in the mc9s08el32 series and mc9s08sl16 series .....................................................19 1.2 mcu block diagram .......................................................................................................... ............20 1.3 system clock di stribution .................................................................................................. ............23 chapter 2 pins and connections 2.1 device pin assi gnment ...................................................................................................... .............25 2.2 recommended system connections ............................................................................................. ..26 2.2.1 power .................................................................................................................... ............26 2.2.2 oscillator ............................................................................................................... ............27 2.2.3 reset .............................................................................................................................. 27 2.2.4 background / mode sel ect (bkgd/ms) ..........................................................................28 2.2.5 general-purpose i/o and peripheral ports ........................................................................28 chapter 3 modes of operation 3.1 introducti on ............................................................................................................... ......................31 3.2 features ................................................................................................................... ........................31 3.3 run mode ................................................................................................................... .....................31 3.4 active backgr ound mode ..................................................................................................... ..........31 3.5 wait mode .................................................................................................................. .....................32 3.6 stop modes ................................................................................................................. .....................32 3.6.1 stop3 mode ............................................................................................................... ........33 3.7 stop2 mode ................................................................................................................. ....................34 3.8 on-chip peripheral modules in stop modes ..................................................................................3 4 chapter 4 memory 4.1 mc9s08el32 series and mc9s08s l16 series memory map ......................................................37 4.2 reset and interrupt vector assignments ..................................................................................... ....38 4.3 register addresses a nd bit assignments ..................................................................................... ...39 4.4 ram ........................................................................................................................ ........................46 4.5 flash and ee prom ....................... .................................................................................... .........47 4.5.1 features ................................................................................................................. ............47 4.5.2 program and erase times .................................................................................................4 7 4.5.3 program and erase command execution .........................................................................48 4.5.4 burst program ex ecution .................................................................................................. 49
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 10 freescale semiconductor section number title page 4.5.5 sector erase abort ....................................................................................................... .....51 4.5.6 access erro rs ............................................................................................................ ........52 4.5.7 block protec tion ......................................................................................................... ......53 4.5.8 vector redire ction ....................................................................................................... .....53 4.5.9 security ................................................................................................................. ............53 4.5.10 eeprom mapping .......................................................................................................... .55 4.5.11 flash and eeprom register s and control bits ..........................................................55 chapter 5 resets, interrupts, and general system control 5.1 introducti on ............................................................................................................... ......................63 5.2 features ................................................................................................................... ........................63 5.3 mcu reset .................................................................................................................. ....................63 5.4 computer operating prope rly (cop) watchdog .............................................................................64 5.5 interrupts ................................................................................................................. ........................65 5.5.1 interrupt stack frame .................................................................................................... ...66 5.5.2 interrupt vectors, sources , and local ma sks ...................................................................67 5.6 low-voltage detect (lvd) system ............................................................................................ ....68 5.6.1 power-on reset op eration ...............................................................................................69 5.6.2 low-voltage detection (lvd ) reset operation ...............................................................69 5.6.3 low-voltage warning (lvw) interrupt operation ...........................................................69 5.7 reset, interrupt, and system contro l registers and control bits ...................................................70 5.7.1 system reset status register (srs) .................................................................................71 5.7.2 system background debug force re set register (sbdfr) ............................................72 5.7.3 system options register 1 (sopt1) ................................................................................73 5.7.4 system options register 2 (sopt2) ................................................................................74 5.7.5 system device identification register (sdidh, sdidl) ................................................75 5.7.6 system power management status a nd control 1 register (spmsc1) ...........................76 5.7.7 system power management status a nd control 2 register (spmsc2) ...........................77 chapter 6 parallel input/output control 6.1 port data and data directio n ............................................................................................... ...........79 6.2 pull-up, slew rate, and drive strength ..................................................................................... .....80 6.3 pin interrupts ............................................................................................................. ......................81 6.3.1 edge only sens itivity .................................................................................................... ...81 6.3.2 edge and level se nsitivity ............................................................................................... 81 6.3.3 pull-up/pull-down resistors .............................................................................................8 2 6.3.4 pin interrupt initi alization ............................................................................................. ....82 6.4 pin behavior in stop modes ................................................................................................. ...........82 6.5 parallel i/o and pin control regi sters ..................................................................................... .......82 6.5.1 port a regi sters ......................................................................................................... .......83
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 11 section number title page 6.5.2 port b regi sters ......................................................................................................... .......87 6.5.3 port c regi sters ......................................................................................................... .......91 chapter 7 central processor unit (s08cpuv3) 7.1 introducti on ............................................................................................................... ......................95 7.1.1 features ................................................................................................................. ............95 7.2 programmer?s model and cpu registers ....................................................................................... 96 7.2.1 accumulator (a) .......................................................................................................... .....96 7.2.2 index register (h:x) ..................................................................................................... ...96 7.2.3 stack pointer (sp) ....................................................................................................... ......97 7.2.4 program counter (pc) ..................................................................................................... .97 7.2.5 condition code register (ccr) .......................................................................................97 7.3 addressing modes ........................................................................................................... ................99 7.3.1 inherent addressing mode (inh) .....................................................................................99 7.3.2 relative addressing mode (rel) ....................................................................................99 7.3.3 immediate addressing mode (imm) ................................................................................99 7.3.4 direct addressing mode (dir) ........................................................................................99 7.3.5 extended addressing mode (ext) ................................................................................100 7.3.6 indexed addressing mode ..............................................................................................100 7.4 special oper ations ......................................................................................................... ................101 7.4.1 reset seque nce ........................................................................................................... ....101 7.4.2 interrupt sequence ....................................................................................................... ...101 7.4.3 wait mode op eration ...................................................................................................... 102 7.4.4 stop mode oper ation ...................................................................................................... 102 7.4.5 bgnd instru ction ......................................................................................................... ..103 7.5 hcs08 instruction set summary .............................................................................................. ....103 chapter 8 internal clock source (s08icsv2) 8.1 introducti on ............................................................................................................... ....................115 8.1.1 module configur ation ..................................................................................................... 115 8.1.2 features ................................................................................................................. ..........117 8.1.3 block diag ram ............................................................................................................ ....117 8.1.4 modes of oper ation ....................................................................................................... .118 8.2 external signal de scription ................................................................................................ ..........119 8.3 register definition ........................................................................................................ ................119 8.3.1 ics control register 1 (icsc1) .....................................................................................120 8.3.2 ics control register 2 (icsc2) .....................................................................................121 8.3.3 ics trim register (icstrm) .........................................................................................122 8.3.4 ics status and control (icssc) .....................................................................................122 8.4 functional description ..................................................................................................... .............123
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 12 freescale semiconductor section number title page 8.4.1 operational modes ........................................................................................................ ..123 8.4.2 mode switch ing ........................................................................................................... ...125 8.4.3 bus frequency di vider ...................................................................................................1 26 8.4.4 low power bit usage .....................................................................................................1 26 8.4.5 internal referen ce clock ................................................................................................1 26 8.4.6 optional external reference clock ................................................................................126 8.4.7 fixed frequency clock ...................................................................................................1 27 chapter 9 5-v analog comparator (s08acmpv2) 9.1 introducti on ............................................................................................................... ....................129 9.1.1 acmpx configuration information ................................................................................129 9.1.2 acmp1/tpm1 configura tion information ....................................................................129 9.1.3 features ................................................................................................................. ..........131 9.1.4 modes of oper ation ....................................................................................................... .131 9.1.5 block diag ram ............................................................................................................ ....132 9.2 external signal de scription ................................................................................................ ..........133 9.3 memory map ................................................................................................................ ................133 9.3.1 register descri ptions .................................................................................................... ..133 9.4 functional description ..................................................................................................... .............135 chapter 10 analog-to-digital converter (s08adcv1) 10.1 introducti on .............................................................................................................. .....................137 10.1.1 channel assignments ..................................................................................................... 137 10.1.2 alternate clock ......................................................................................................... ......138 10.1.3 hardware trigger ........................................................................................................ ....138 10.1.4 temperature sensor ...................................................................................................... ..138 10.1.5 features ................................................................................................................ ...........141 10.1.6 block diag ram ........................................................................................................... .....141 10.2 external signal de scription ............................................................................................... ...........142 10.2.1 analog power (v ddad ) ..................................................................................................143 10.2.2 analog ground (v ssad ) .................................................................................................143 10.2.3 voltage reference high (v refh ) ...................................................................................143 10.2.4 voltage reference low (v refl ) ....................................................................................143 10.2.5 analog channel inputs (adx) ........................................................................................143 10.3 register definition ....................................................................................................... .................143 10.3.1 status and control regi ster 1 (adcsc1) ......................................................................143 10.3.2 status and control regi ster 2 (adcsc2) ......................................................................145 10.3.3 data result high register (adcrh) .............................................................................146 10.3.4 data result low regi ster (adcrl) ..............................................................................146 10.3.5 compare value high register (adccvh) ....................................................................147
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 13 section number title page 10.3.6 compare value low register (adccvl) .....................................................................147 10.3.7 configuration regist er (adccfg) ................................................................................147 10.3.8 pin control 1 regist er (apctl1) ..................................................................................149 10.3.9 pin control 2 regist er (apctl2) ..................................................................................150 10.3.10pin control 3 regist er (apctl3) ..................................................................................151 10.4 functional description .................................................................................................... ..............152 10.4.1 clock select and di vide control ....................................................................................152 10.4.2 input select and pin control ...........................................................................................1 53 10.4.3 hardware trigger ........................................................................................................ ....153 10.4.4 conversion c ontrol ...................................................................................................... ...153 10.4.5 automatic compare function .........................................................................................156 10.4.6 mcu wait mode op eration ............................................................................................156 10.4.7 mcu stop3 mode operation ..........................................................................................156 10.4.8 mcu stop1 and stop2 mode operation .........................................................................157 10.5 initialization in formation ................................................................................................ ..............157 10.5.1 adc module initializa tion example .............................................................................157 10.6 application information ................................................................................................... .............159 10.6.1 external pins and routing ..............................................................................................1 59 10.6.2 sources of error ........................................................................................................ ......161 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introducti on .............................................................................................................. .....................165 11.1.1 module confi guration .................................................................................................... .165 11.1.2 features ................................................................................................................ ...........167 11.1.3 modes of op eration ...................................................................................................... ..167 11.1.4 block diag ram ........................................................................................................... .....168 11.2 external signal description ............................................................................................... ...........168 11.2.1 scl ? serial clock line ...............................................................................................16 8 11.2.2 sda ? serial da ta line ................................................................................................16 8 11.3 register definition ....................................................................................................... .................168 11.3.1 iic address register (iica) ...........................................................................................16 9 11.3.2 iic frequency divider register (iicf) ..........................................................................169 11.3.3 iic control regist er (iicc1) ..........................................................................................17 2 11.3.4 iic status regist er (iics) .............................................................................................. .172 11.3.5 iic data i/o regi ster (iicd) ..........................................................................................17 3 11.3.6 iic control register 2 (iicc2) .......................................................................................174 11.4 functional description .................................................................................................... ..............175 11.4.1 iic protocol ............................................................................................................ .........175 11.4.2 10-bit address .......................................................................................................... .......178 11.4.3 general call address .................................................................................................... ..179 11.5 resets .................................................................................................................... ........................179
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 14 freescale semiconductor section number title page 11.6 interrupts ................................................................................................................ .......................179 11.6.1 byte transfer interrupt ................................................................................................. ...179 11.6.2 address detect interrupt ................................................................................................ .180 11.6.3 arbitration lost interrupt .............................................................................................. ..180 11.7 initialization/appli cation inform ation .................................................................................... ......181 chapter 12 slave lin interface controller (s08slicv1) 12.1 introducti on .............................................................................................................. .....................185 12.1.1 features ................................................................................................................ ...........187 12.1.2 modes of oper ation ...................................................................................................... ..188 12.1.3 block diag ram ........................................................................................................... .....191 12.2 external signal de scription ............................................................................................... ...........191 12.2.1 slctx ? slic transmit pin ........................................................................................191 12.2.2 slcrx ? slic receive pin ..........................................................................................191 12.3 register definition ....................................................................................................... .................191 12.3.1 slic control regist er 1 (slcc1 ) ..................................................................................191 12.3.2 slic control regist er 2 (slcc2 ) ..................................................................................193 12.3.3 slic bit time registers (slcbth, slcbtl) .............................................................195 12.3.4 slic status regist er (slcs) ..........................................................................................196 12.3.5 slic state vector register (slcsv) .............................................................................197 12.3.6 slic data length code register (slcdlc) ................................................................202 12.3.7 slic identifier and data registers (slcid, slcd7-slcd0) ......................................203 12.4 functional description .................................................................................................... ..............204 12.5 interrupts ................................................................................................................ .......................204 12.5.1 slic during break interrupts ........................................................................................204 12.6 initialization/applicat ion informat ion .................................................................................... ......204 12.6.1 lin message fram e header ...........................................................................................205 12.6.2 lin data field .......................................................................................................... ......205 12.6.3 lin checksum field ...................................................................................................... .206 12.6.4 slic module cons traints ...............................................................................................20 6 12.6.5 slcsv interrupt handling .. ...........................................................................................206 12.6.6 slic module initializa tion procedure ............................................................................206 12.6.7 handling lin message headers .....................................................................................208 12.6.8 handling command message frames ............................................................................211 12.6.9 handling request lin me ssage frames ........................................................................214 12.6.10handling imsg to mini mize interr upts .........................................................................218 12.6.11sleep and wakeup operation ..........................................................................................219 12.6.12polling operat ion ...................................................................................................... ......219 12.6.13lin data integrity checking methods ...........................................................................219 12.6.14high-speed lin op eration .............................................................................................22 0 12.6.15bit error detection and physical layer delay ...............................................................223
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 15 section number title page 12.6.16byte transfer mode operation .......................................................................................224 12.6.17oscillator trimming with slic ......................................................................................228 12.6.18digital receive filter ......................................................................................................230 chapter 13 serial peripheral interface (s08spiv3) 13.1 introducti on .............................................................................................................. .....................233 13.1.1 features ................................................................................................................ ...........235 13.1.2 block diagra ms .......................................................................................................... ....235 13.1.3 spi baud rate generation ..............................................................................................23 7 13.2 external signal de scription ............................................................................................... ...........238 13.2.1 spsck ? spi serial clock ............................................................................................238 13.2.2 mosi ? master data out, slave data in ......................................................................238 13.2.3 miso ? master data i n, slave data out ......................................................................238 13.2.4 ss ? slave select ..........................................................................................................238 13.3 modes of op eration ........................................................................................................ ...............239 13.3.1 spi in stop modes ....................................................................................................... ...239 13.4 register definition ....................................................................................................... .................239 13.4.1 spi control register 1 (spic1) ......................................................................................239 13.4.2 spi control register 2 (spic2) ......................................................................................240 13.4.3 spi baud rate register (spibr) ....................................................................................241 13.4.4 spi status register (spis) .............................................................................................. 242 13.4.5 spi data register (spid) ...............................................................................................2 43 13.5 functional description .................................................................................................... ..............244 13.5.1 spi clock fo rmats ....................................................................................................... ...244 13.5.2 spi interrupts .......................................................................................................... ........247 13.5.3 mode fault de tection .................................................................................................... .247 chapter 14 serial communications interface (s08sciv4) 14.1 introducti on .............................................................................................................. .....................249 14.1.1 features ................................................................................................................ ...........251 14.1.2 modes of oper ation ...................................................................................................... ..251 14.1.3 block diag ram ........................................................................................................... .....252 14.2 register definition ....................................................................................................... .................254 14.2.1 sci baud rate registers (s cixbdh, scixbdl) ..........................................................254 14.2.2 sci control register 1 (scixc1) ...................................................................................255 14.2.3 sci control register 2 (scixc2) ...................................................................................256 14.2.4 sci status register 1 (scixs1) ......................................................................................257 14.2.5 sci status register 2 (scixs2) ......................................................................................259 14.2.6 sci control register 3 (scixc3) ...................................................................................260 14.2.7 sci data register (scixd) .............................................................................................26 1
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 16 freescale semiconductor section number title page 14.3 functional description .................................................................................................... ..............261 14.3.1 baud rate gene ration .......... .......................................................................................... .261 14.3.2 transmitter functiona l descriptio n ................................................................................262 14.3.3 receiver functional description ....................................................................................263 14.3.4 interrupts and stat us flags ............................................................................................. .265 14.3.5 additional sci f unctions ...............................................................................................2 66 chapter 15 real-time counter (s08rtcv1) 15.1 introducti on .............................................................................................................. .....................269 15.1.1 features ................................................................................................................ ...........272 15.1.2 modes of oper ation ...................................................................................................... ..272 15.1.3 block diag ram ........................................................................................................... .....273 15.2 external signal de scription ............................................................................................... ...........273 15.3 register definition ....................................................................................................... .................273 15.3.1 rtc status and control register (rtc sc) ....................................................................274 15.3.2 rtc counter register (rtccnt) ..................................................................................275 15.3.3 rtc modulo register (rtcmod) ................................................................................275 15.4 functional description .................................................................................................... ..............275 15.4.1 rtc operation ex ample .................................................................................................27 6 15.5 initialization/applicat ion informat ion .................................................................................... ......277 chapter 16 timer pulse-width modulator (s08tpmv2) 16.1 introducti on .............................................................................................................. .....................279 16.1.1 features ................................................................................................................ ...........281 16.1.2 modes of oper ation ...................................................................................................... ..281 16.1.3 block diag ram ........................................................................................................... .....282 16.2 signal desc ription ........................................................................................................ .................284 16.2.1 detailed signal de scriptions ..........................................................................................28 4 16.3 register definition ....................................................................................................... .................288 16.3.1 tpm status and control re gister (tpmxs c) ................................................................288 16.3.2 tpm-counter registers (t pmxcnth:tpmxcntl) ....................................................289 16.3.3 tpm counter modulo registers (tpmxmodh:tpmxmodl) ....................................290 16.3.4 tpm channel n status and control register (tpmxcnsc) ..........................................291 16.3.5 tpm channel value register s (tpmxcnvh:tpmxcnvl) ..........................................293 16.4 functional description .................................................................................................... ..............294 16.4.1 counter ................................................................................................................. ...........295 16.4.2 channel mode se lection ...... ...........................................................................................2 97 16.5 reset overview ............................................................................................................ .................300 16.5.1 general ................................................................................................................. ...........300 16.5.2 description of reset operation .......................................................................................300
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 17 section number title page 16.6 interrupts ................................................................................................................ .......................300 16.6.1 general ................................................................................................................. ...........300 16.6.2 description of interr upt operation .................................................................................301 16.7 the differences from tpm v2 to tpm v3 ....................................................................................3 02 chapter 17 development support 17.1 introducti on .............................................................................................................. .....................307 17.1.1 forcing active background ............................................................................................307 17.1.2 features ................................................................................................................ ...........310 17.2 background debug contro ller (bdc) ......................................................................................... .310 17.2.1 bkgd pin descri ption ...................................................................................................3 11 17.2.2 communication details ..................................................................................................3 12 17.2.3 bdc commands ............................................................................................................ .316 17.2.4 bdc hardware br eakpoint .............................................................................................318 17.3 on-chip debug syst em (dbg) ................................................................................................ ....319 17.3.1 comparators a and b ..................................................................................................... 319 17.3.2 bus capture information and fifo operation ...............................................................319 17.3.3 change-of-flow in formation ..........................................................................................320 17.3.4 tag vs. force breakpoint s and triggers .........................................................................320 17.3.5 trigger modes ........................................................................................................... ......321 17.3.6 hardware breakpoints .................................................................................................... 323 17.4 register definition ....................................................................................................... .................323 17.4.1 bdc registers and control bits .....................................................................................323 17.4.2 system background debug force re set register (sbdfr) ..........................................325 17.4.3 dbg registers and c ontrol bits .....................................................................................326 appendix a electrical characteristics a.1 introducti on ............................................................................................................... ....................331 a.2 parameter clas sification ................................................................................................... .............331 a.3 absolute maximu m ratings ................................................................................................... .......331 a.4 thermal charac teristic s .................................................................................................... .............332 a.5 esd protection and latch-up immunity ......................................................................................3 33 a.6 dc characteristics ......................................................................................................... ................334 a.7 supply current char acteristics ............................................................................................. .........338 a.8 external oscillator (xosc) characteristics ................................................................................. 341 a.9 internal clock source (i cs) characteri stics ................................................................................ .342 a.10 analog comparator (acmp) electricals ...................................................................................... 343 a.11 adc character istics ....................................................................................................... ...............344 a.12 ac character istics ........................................................................................................ .................347 a.12.1 control ti ming .......................................................................................................... .....347
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 18 freescale semiconductor section number title page a.12.2 tpm/mtim modul e timing ..........................................................................................348 a.12.3 spi ..................................................................................................................... ..............349 a.13 flash and eeprom specifications ........................................................................................... ....352 a.14 emc performance ........................................................................................................... ..............353 a.14.1 radiated em issions ...................................................................................................... ...353 a.14.2 conducted transient susceptibility ................................................................................354 appendix b ordering information an d mechanical drawings b.1 ordering information ....................................................................................................... .............355 b.1.1 device numbering scheme . ...........................................................................................355 b.2 mechanical dr awings ........................................................................................................ ............356
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 19 chapter 1 device overview the mc9s08el32 series and mc9s08sl16 series ar e members of the low-cost, high-performance hcs08 family of 8-bit mi crocontroller units (mcus). all mcus in the family use the enhanced hcs08 core and are available with a variety of modules, memory size s, memory types, and package types. 1.1 devices in the mc9s08el32 series and mc9s08sl16 series table 1-1 summarizes the feature set available in th e mc9s08el32 series and mc9s08sl16 series of mcus. t table 1-1. mc9s08el32 series and mc9s08sl16 series features by mcu and package feature 9s08el32 9s08el16 9s08sl16 9s08sl8 flash size (bytes) 32768 16384 16384 8192 ram size (bytes) 1024 512 eeprom size (bytes) 512 256 pin quantity 2820282028202820 package type tssop tssop tssop tssop tssop tssop tssop tssop port interrupts 1612161216121612 acmp1 yes yes acmp2 yes no yes no no adc channels 1612161216121612 dbg yes yes ics yes yes iic yes yes rtc yes yes sci yes yes slic yes yes spi yes yes tpm1 channels 4 2 tpm2 channels 2 2 xosc yes yes
chapter 1 device overview mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 20 freescale semiconductor 1.2 mcu block diagram the block diagram in figure 1-1 shows the structure of the mc9s08 el32 series. not all features are available on all devices in all packages. see table 1-1 for details. figure 1-1. mc9s08el32 and mc9s08el16 block diagram v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
chapter 1 device overview mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 21 the block diagram in figure 1-2 shows the structure of the mc9s08sl16 series. figure 1-2. mc9s08sl16 and mc9s08sl8 block diagram v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 16k / 8k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 512 bytes interface (sci) serial communications xtal extal 2-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/adp11 ptc4/pic4/adp12 ptc5/pic5/adp13 ptc2/pic2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/adp14 v dd bkp int user eeprom 256 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out 0 1 1 0 rxd txd tx rx
chapter 1 device overview mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 22 freescale semiconductor table 1-2 provides the functional vers ion of the on-chip modules table 1-2. module versions module version central processor unit (cpu) 3 internal clock source (ics) 2 5-v analog comparator (acmp_5v) 2 analog-to-digital converter (adc) 1 inter-integrated circuit (iic) 2 slave lin interface controller (slic) 1 serial peripheral interface (spi) 3 serial communications interface (sci) 4 real-time counter (rtc) 1 timer pulse width modulator (tpm) 2 on-chip ice debug (dbg) 2
chapter 1 device overview mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 23 1.3 system clock distribution figure 1-3 shows a simplified clock connection diagram. some modules in the mcu have selectable clock inputs as shown. the clock inputs to the modules indica te the clock(s) that are used to drive the module function. the following defines the clocks used in this mcu: ? busclk ? the frequency of the bus is always half of icsout. ? icsout ? primary output of the ic s and is twice the bus frequency. ? icslclk ? development tools can select this clock source to speed up bdc communications in systems where the bus clock is configur ed to run at a very slow frequency. ? icserclk ? external reference clock can be selected as the rtc clock source and as the alternate clock for the adc module. ? icsirclk ? internal reference clock can be selected as the rtc clock source. ? icsffclk ? fixed frequency clock can be selected as clock source for the tpm1 and tpm2 modules. ? lpo ? independent 1-khz clock th at can be selected as the s ource for the cop and rtc modules. ? tclk ? external input clock sour ce for tpm1 and tpm2 and is referenced as tpmclk in tpm chapters. figure 1-3. system clock distribution diagram tpm1 tpm2 sci slic bdc cpu adc iic flash ics icsout 2 busclk icslclk icserclk cop * the fixed frequency clock (ffclk) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. flash and eeprom have frequency requirements for program and erase operation. see the electricals appendix for details. adc has min and max frequency requirements. see the adc chapter and electricals appendix for details. xosc extal xtal eeprom spi ffclk* icsffclk rtc 1 khz lpo tclk icsirclk 2
chapter 1 device overview mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 24 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 25 chapter 2 pins and connections this section describes signals that connect to package pins. it incl udes pinout diagrams, recommended system connections, and detail ed discussions of signals. 2.1 device pin assignment this section describes pin assignm ents for the mc9s08el32 series a nd mc9s08sl16 series devices. not all features are available in all devices. see table 1-1 for details. figure 2-1. 28-pin tssop figure 2-2. 20-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ptc6/pic6/acmp2+/adp14 ptc7/pic7/acmp2?/adp15 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta1/pia1/tpm2ch0/acmp1?/adp1 pta2/pia2/sda/rxd/acmp1o/adp2 pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta7/tpm2ch1 ptb0/pib0/slrxd/rxd/adp4 ptb1/pib1/sltxd/txd/adp5 ptb2/pib2/sda/spsck/adp6 ptb3/pib3/scl/mosi/adp7 ptc0/pic0/tpm1ch0/adp8 ptc1/pic1/tpm1ch1/adp9 ptc5/pic5/acmp2o/adp13 ptc4/pic4/adp12 reset bkgd/ms v dd v dda /v refh v ssa /v refl v ss ptb7/scl/extal ptb6/sda/xtal ptb5/tpm1ch1/ss ptb4/tpm2ch1/miso ptc3/pic3/tpm1ch3/adp11 ptc2/pic2/tpm1ch2/adp10 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin tssop 1 2 3 4 5 6 7 8 9 10 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta1/pia1/tpm2ch0/acmp1?/adp1 pta2/pia2/sda/rxd/acmp1o/adp2 pta3/pia3/scl/txd/adp3 ptb0/pib0/slrxd/rxd/adp4 ptb1/pib1/sltxd/txd/adp5 ptb2/pib2/sda/spsck/adp6 ptb3/pib3/scl/mosi/adp7 ptc0/pic0/tpm1ch0/adp8 ptc1/pic1/tpm1ch1/adp9 reset bkgd/ms v dd /v dda /v refh v ss /v ssa /v refl ptb7/scl/extal ptb6/sda/xtal ptb5/tpm1ch1/ss ptb4/tpm2ch1/miso ptc3/pic3/tpm1ch3/adp11 ptc2/pic2/tpm1ch2/adp10 20 19 18 17 16 15 14 13 12 11 20-pin tssop
chapter 2 pins and connections mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 26 freescale semiconductor 2.2 recommended system connections figure 2-3 shows pin connections that are common to mc9s08el32 series and mc9s08sl16 series application systems. figure 2-3. basic system connections 2.2.1 power v dd and v ss are the primary power supply pi ns for the mcu. this voltage source supplies power to all i/o buffer circuitry and to an intern al voltage regulator. the internal vol tage regulator provides a regulated lower-voltage source to the cpu and ot her internal circuitry of the mcu. typically, application systems have two separate capac itors across the power pins. in this case, there should be a bulk electrolytic capacitor, such as a 10- f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1- f ceramic bypass capacitor located as near to the mcu power pins as practical to suppress high-frequenc y noise. each pin must have a bypass capacitor for best noise suppression. v dda and v ssa are the analog power supply pins for the mcu. this voltage source supplies power to the adc module. a 0.1- f ceramic bypass capacitor should be located as near to the mcu power pins as practical to suppress hi gh-frequency noise. the v refh and v refl pins are the voltage reference high and voltage reference low inputs, re spectively, for the adc module. bkgd/ms reset optional manual reset v dd background header system power port b ptb0/pib0/slrxd/rxd/adp4 ptb1/pib1/sltxd/txd/adp5 ptb2/pib2/sda/spsck/adp6 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso2 ptb5/tpm1ch1/ss ptb6/sda/xtal ptb7/scl/extal port c ptc0/pic0/tpm1ch0/adp8 ptc1/pic1/tpm1ch1/adp9 ptc2/pic2/tpm1ch2/adp10 ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc6/pic6/acmp2+/adp14 mc9s08el32 v dda /v refh v ssa /v refl v ss v dd ptc7/pic7/acmp2?/adp15 c by 0.1 f c blk 10 f + 5 v + c2 c1 x1 r f r s port a pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta1/pia1/tpm2ch0/acmp1?/adp1 pta2/pia2/sda/rxd/acmp1o/adp2 pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta7/tpm2ch1 v dd 4.7 k ?10 k 0.1 f r pu r pu c by 0.1 f
chapter 2 pins and connections mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 27 2.2.2 oscillator immediately after reset, the mcu uses an intern ally generated clock provi ded by the clock source generator (ics) module. this internal clock source is used during reset startup and can be enabled as the clock source for stop r ecovery to avoid the need for a long crysta l startup delay. for more information on the ics, see chapter 8, ?internal clock source (s08icsv2) .? the oscillator (xosc) in this mcu is a pierce os cillator that can accommodate a crystal or ceramic resonator. rather than a crystal or ceramic resonator, an external osci llator can be connected to the extal input pin. refer to figure 2-3 for the following discussion. r s (when used) and r f should be low-inductance resistors such as carbon composition resistors. wire-wound resi stors, and some metal film resistors, have too much inductance. c1 and c2 nor mally should be high-qual ity ceramic capacitors that are specifically designed for high-freque ncy applications. r f is used to provide a bias path to keep the extal in put in its linear range duri ng crystal startup; its value is not generally critical . typical systems use 1 m to 10 m . higher values are sens itive to humidity and lower values reduce gain and (in ex treme cases) could prevent startup. c1 and c2 are typically in the 5-pf to 25-pf range and are chosen to match the requirements of a specific crystal or resonator. be sure to take into acc ount printed circuit board (p cb) capacitance and mcu pin capacitance when selecting c1 and c2. the crystal manufacturer typically speci fies a load capacitance which is the series combination of c1 and c2 (w hich are usually the same size). as a first-order approximation, use 10 pf as an estimate of combined pin and pcb capacitance for each oscillator pin (extal and xtal). 2.2.3 reset reset is a dedicated pin with a built in pull-up device. it has input hysteresis and an open drain output. since the pin does not ha ve a clamp diode to v dd , it should not be driven above v dd . internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. this pin is normally connected to the standa rd 6-pin background debug connector so a development system can directly reset the mcu system. if desired, a manual external reset can be a dded by supplying a simple switch to ground (pull reset pin low to force a reset). whenever any reset is initiated (whether from an exte rnal signal or from an in ternal system), the reset pin is driven low for about 66 bus cy cles. the reset circuitry decodes th e cause of reset and records it by setting a corresponding bit in the syst em reset status register (srs). note this pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on th e internally-pulled-up reset pin is not pulled to v dd . the internal gates connected to this pin are pulled to v dd . if the reset pin is required to drive to a v dd level, use an external pullup.
chapter 2 pins and connections mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 28 freescale semiconductor note in emc-sensitive applications, us e an external rc filter on reset . see figure 2-3 for an example. 2.2.4 background / mode select (bkgd/ms) while in reset, the bkgd/ms pin f unctions as a mode select pin. imme diately after reset rises, the pin functions as the backgr ound pin and can be used for backgr ound debug communication. while functioning as a background or mode sel ect pin, the pin includes an internal pul l-up device, input hysteresis, a standard output driver, and no output slew rate control. if nothing is connected to this pi n, the mcu will enter normal operating m ode at the rising edge of reset. if a debug system is connected to the 6-pin st andard background debug header, it can hold bkgd low during the rising edge of reset which fo rces the mcu to active background mode. the bkgd/ms pin is used primarily for background de bug controller (bdc) communications using a custom protocol that uses 16 clock cycles of the ta rget mcu?s bdc clock per bi t time. the target mcu?s bdc clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the bkgd/ms pin that could in terfere with background serial communications. although the bkgd/ms pin is a ps eudo open-drain pin, the background debug communica tion protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall times on the bkgd/ms pin. 2.2.5 general-purpose i/o and peripheral ports the mc9s08el32 series and mc9s08sl16 series of mcus support up to 22 general-purpose i/o pins which are shared with on-chip peripheral f unctions (timers, seri al i/o, adc, etc.). when a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and en able or disable slew rate control. when a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-up device. immediatel y after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pull-up devices disabled. when an on-chip peripheral system is controlling a pin, data direction c ontrol bits still determine what is read from port data registers even though the periphe ral module controls the pi n direction by controlling the enable for the pin?s output buffer. for information about controlling these pins as general-purpose i/o pins, see chapter 6, ?parallel input/output control .? note to avoid extra current drain from floa ting input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not float.
chapter 2 pins and connections mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 29 table 2-1. pin availability by package pin-count pin number <-- lowest priority --> highest 28 20 port pin alt 1 alt 2 alt3 alt4 alt5 1 ? ptc5 pic5 acmp2o adp13 2 ? ptc4 pic4 adp12 3 1 reset 1 1 pin does not contain a clamp diode to v dd and should not be driven above v dd . 4 2 bkgd 5 3 v dd 6v dda v refh 7 4 v ssa v refl 8v ss 9 5 ptb7 scl 2 2 iic pins can be repositioned using iicps in sopt1, default reset locations are on pta2 and pta3. extal 10 6 ptb6 sda 2 xtal 11 7 ptb5 tpm1ch1 3 3 tpm1ch1 pin can be repositioned using t1ch1ps in sopt2, default reset location is on ptb5. ss 12 8 ptb4 tpm2ch1 4 4 tpm2ch1 pin can be repositioned using t2ch1ps in sopt2, default reset locations are on ptb4. miso 13 9 ptc3 pic3 tpm1ch3 adp11 14 10 ptc2 pic2 tpm1ch2 adp10 15 11 ptc1 pic1 tpm1ch1 3 adp9 16 12 ptc0 pic0 tpm1ch0 5 5 tpm1ch0 pin can be repositioned using t1ch0ps in sopt2, default reset locations are on pta0. adp8 17 13 ptb3 pib3 scl 2 mosi adp7 18 14 ptb2 pib2 sda 2 spsck adp6 19 15 ptb1 pib1 sltxd txd 6 6 sci pins can be repositioned using scips in sopt1, default reset locations are on ptb0 and ptb1. adp5 20 16 ptb0 pib0 slrxd rxd 6 adp4 21 ? pta7 tpm2ch1 4 22 ? pta6 tpm2ch0 7 7 tpm2ch0 pin can be repositioned using t2ch0ps in sopt2, default reset locations are on pta1. 23 17 pta3 pia3 scl 2 txd 6 adp3 24 18 pta2 pia2 sda 2 rxd 6 acmp1o adp2 25 19 pta1 pia1 tpm2ch0 7 acmp1? 8 8 if acmp and adc are both enabled, both will have access to the pin. adp1 8 26 20 pta0 pia0 tpm1ch0 5 tclk acmp1+ 8 adp0 8 27 ? ptc7 pic7 acmp2? 8 adp15 8 28 ? ptc6 pic6 acmp2+ 8 adp14 8
chapter 2 pins and connections mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 30 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 31 chapter 3 modes of operation 3.1 introduction the operating modes of the mc9s08el 32 series and mc9s08sl16 series ar e described in this chapter. entry into each mode, exit from e ach mode, and functionality while in each of the modes is described. 3.2 features ? active background mode for code development ? wait mode ? cpu shuts down to conserve power; system clocks are r unning and full regulation is maintained ? stop modes ? system clocks are stoppe d and voltage regulator is in standby ? stop3 ? all internal circuits are powered for fast recovery; ram and register contents are retained ? stop2 ? partial power down of internal circuits; ram content is retained 3.3 run mode this is the normal operating mode for the mc9s08el 32 series and mc9s08sl16 series. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode, the cpu executes code from internal memory with exec ution beginning at the address fetc hed from memory at 0xfffe?0xffff after reset. 3.4 active background mode the active background mode functions are manage d through the background de bug controller (bdc) in the hcs08 core. the bdc, together with the on-chip debug module (dbg), provide the means for analyzing mcu operation duri ng software development. active background mode is entered in any of five ways: ? when the bkgd/ms pin is low at the rising edge of reset ? when a background command is received through the bkgd/ms pin ? when a bgnd instruction is executed ? when encountering a bdc breakpoint ? when encountering a dbg breakpoint after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructi ons from the user application program.
chapter 3 modes of operation mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 32 freescale semiconductor background commands are of two types: ? non-intrusive commands, defined as commands that can be issu ed while the user program is running. non-intrusive commands can be issued through the bkgd/ms pin while the mcu is in run mode; non-intrusive commands can also be executed when the mcu is in the active background mode. non-intrusive commands include: ? memory access commands ? memory-access-with-status commands ? bdc register access commands ? the background command ? active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: ? read or write cpu registers ? trace one user program instruction at a time ? leave active background mode to return to the user application program (go) the active background mode is used to program a bootloader or user a pplication program into the flash program memory before the mcu is operated in r un mode for the first time. when the mc9s08el32 series and mc9s08sl16 series is shipped from the freescale semiconductor factory, the flash program memory is erased by default unless specifically noted so th ere is no program that could be executed in run mode until the fl ash memory is initially programmed. the active background mode can also be used to erase and repr ogram the flash memory after it has been previously programmed. for additional information about the active background mode, refer to the development support chapter. 3.5 wait mode wait mode is entered by executing a wait instruction. u pon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking opera tions leading to the in terrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background co mmand and memory-access-with-s tatus commands are available when the mcu is in wait mode. the memory-access- with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode. 3.6 stop modes one of two stop modes is entered upon execution of a stop instruction when the stope bit in sopt1 register is set. in both stop modes, all internal clocks are halted. the ic s module can be configured to leave the reference clocks running. see chapter 8, ?internal cl ock source (s08icsv2) ,? for more information.
chapter 3 modes of operation mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 33 table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. the selected mode is entered fo llowing the execution of a stop instruction. 3.6.1 stop3 mode stop3 mode is entered by executing a stop inst ruction under the cond itions as shown in table 3-1 . the states of all of the internal re gisters and logic, ram contents, a nd i/o pin states are maintained. exit from stop3 is done by asserting reset , or an asynchronous interrupt pin. the asynchrono us interrupt pins are pia0-pia3, pib0 -pib3, a nd pic0-pic7. exit from stop3 can also be done by the low-voltage detection (lvd) reset, the low-vo ltage warning (lvw) interrupt, the adc conversion complete interrupt, the analog comparator (acmp) interrupt, the real -time counter (rtc) interrupt, the slic wake-up interrupt, or the sci receiver interrupt. if stop3 is exited by means of the reset pin, the mcu will be reset a nd operation will resume after fetching the reset vector. exit by m eans of an asynchronous interrupt, analog comparator interrupt, or the real-time interrupt will resu lt in the mcu fetching the a ppropriate interrupt vector. 3.6.1.1 lvd enabled in stop mode the lvd system is capable of genera ting either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enable d in stop (lvde and lvds e bits in spmsc1 both set) at the time the cpu executes a stop instruction, then the voltage regulator remains active during stop mode. for the adc to operate the lvd must be left enabled when entering stop3. 3.6.1.2 active bdm enabled in stop mode entry into the active bac kground mode from run mode is enabled if enbdm in bdcscr is set. this register is described in chapter 17, ?development support .? if enbdm is set when the cpu executes a stop instruction, the system clocks to the bac kground debug logic remain active when the mcu enters stop mode. because of this, bac kground debug communication remains possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. table 3-1. stop mode selection stope enbdm 1 1 enbdm is located in the bdcscr, which is only accessible through bdc commands, see section 17.4.1.1, ?bdc status and control register (bdcscr) ?. lv d e lv d s e p p d c s t o p m o d e 0 x x x stop modes disabled; illegal opcode reset if stop instruction executed 1 1 x x stop3 with bdm enabled 2 2 when in stop3 mode with bdm enabled, the s idd will be near r idd levels because internal clocks are enabled. 1 0 both bits must be 1 0 stop3 with voltage regulator active 1 0 either bit a 0 0 stop3 1 0 either bit a 0 1 stop2
chapter 3 modes of operation mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 34 freescale semiconductor most background commands are not available in stop mode. the memo ry-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. af ter entering background de bug mode, all background commands are available. 3.7 stop2 mode stop2 mode is entered by executing a stop in struction under the c onditions as shown in table 3-1 . most of the internal circuitry of the mcu is powered of f in stop2 with the exception of the ram. upon entering stop2, all i/o pin control signals are latched so that the pins retain their states during stop2. exit from stop2 is perfor med by asserting reset on the mcu. in addition, the real-time counter (rtc) can wake the mcu from stop2, if enabled. upon wake-up from stop2 mode, the mcu starts up as from a power-on reset (por): ? all module control and status registers are reset ? the lvd reset function is enabled and th e mcu remains in th e reset state if v dd is below the lvd trip point (low trip poi nt selected due to por) ? the cpu takes the reset vector in addition to the above, upon waking up from stop2, the ppd f bit in spmsc2 is set. this flag is used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latched until a 1 is written to ppdack in spmsc2. to maintain i/o states for pins th at were configured as general-purpose i/o before entering stop2, the user must restore the contents of the i/ o port registers, which have been sa ved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the pins will switch to th eir reset states when ppdack is written. for pins that were configured as peripheral i/o, the user must reconfigure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.8 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal periphera l modules are stopped. even in the exception case (enbdm = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halte d to reduce power consumption. refer to section 3.7, ?stop2 mode ? and section 3.6.1, ?stop3 mode ? for specific information on sy stem behavior in stop modes.
chapter 3 modes of operation mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 35 table 3-2. stop mode behavior peripheral mode stop2 stop3 cpu off standby ram standby standby flash/eeprom off standby parallel port registers off standby acmpx off optionally on 1 1 lvd must be enabled, else in standby. adc off optionally on 2 2 asynchronous adc clock and lvd must be enabled, else in standby. ics off optionally on 3 3 irclken and irefsten must be set in icsc1, else in standby. iic off standby rtc off optionally on 4 4 rtc must be enabled, else in standby. sci off standby slic off standby spi off standby tpmx off standby voltage regulator standby standby xosc off optionally on 5 5 erclken and erefsten must be set in icsc2, else in standby. for high frequency range (range in icsc2 set), the lvd must be enabled in stop3. i/o pins states held states held
chapter 3 modes of operation mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 36 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 37 chapter 4 memory 4.1 mc9s08el32 series and mc9s08sl16 series memory map as shown in figure 4-1 , on-chip memory in the mc9s08el32 series and mc9s 08sl16 series consists of ram, eeprom, and flash program memory for nonvolatile data stor age, and i/o an d control/status registers. the registers ar e divided into three groups: ? direct-page registers (0x0000 through 0x007f) ? high-page registers (0x1800 through 0x18ff) ? nonvolatile registers (0xffb0 through 0xffbf) figure 4-1. mc9s08el32 series and mc9s08sl16 series memory map direct page registers ram 1024 bytes 0x0000 0x007f 0x0080 0x047f 0x1800 0x17ff 0x18ff 0x1900 0xffff 0x1700 mc9s08el32 0x7fff 0x8000 128 bytes high page registers 256 bytes flash 32768 bytes unimplemented 0x0480 0x16ff 4736 bytes unimplemented 26368 bytes eeprom 2 x 256 bytes direct page registers ram 1024 bytes 0x0000 0x007f 0x0080 0x047f 0x1800 0x17ff 0x18ff 0x1900 0xffff 0x1700 mc9s08el16 0x7fff 0x8000 128 bytes high page registers 256 bytes flash 16384 bytes unimplemented 0x0480 0x16ff 4736 bytes unimplemented 26368 bytes eeprom 2 x 256 bytes reserved 0xbfff 0xc000 16384 bytes direct page registers ram 512 bytes 0x0000 0x007f 0x0080 0x027f 0x1800 0x17ff 0x18ff 0x1900 0xffff 0x1780 mc9s08sl16 0x7fff 0x8000 128 bytes high page registers 256 bytes flash 16384 bytes unimplemented 0x0280 0x177f 5376 bytes unimplemented 26368 bytes eeprom 2 x 128 bytes reserved 0xbfff 0xc000 16384 bytes direct page registers ram 512 bytes 0x0000 0x007f 0x0080 0x027f 0x1800 0x17ff 0x18ff 0x1900 0xffff 0x1780 mc9s08sl8 0x7fff 0x8000 128 bytes high page registers 256 bytes flash 8192 bytes unimplemented 0x0280 0x177f 5376 bytes unimplemented 26368 bytes eeprom 2 x 128 bytes reserved 0xdfff 0xe000 24576 bytes
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 38 freescale semiconductor 4.2 reset and interrupt vector assignments table 4-1 shows address assignments for reset and interrupt vectors. th e vector names shown in this table are the labels used in the freesca le semiconductor provided equate f ile for the mc9s08el32 series and mc9s08sl16 series. vector addresses for excluded features are reserved. table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:0xffc1 acmp2 vacmp2 0xffc2:0xffc3 acmp1 vacmp1 0xffc4:0xffc5 reserved ? 0xffc6:0xffc7 reserved ? 0xffc8:0xffc9 reserved ? 0xffca:0xffcb reserved ? 0xffcc:0xffcd rtc vrtc 0xffce:0xffcf iic viic 0xffd0:0xffd1 adc conversion vadc 0xffd2:0xffd3 port c vportc 0xffd4:0xffd5 port b vportb 0xffd6:0xffd7 port a vporta 0xffd8:0xffd9 slic vslic 0xffda:0xffdb sci transmit vscitx 0xffdc:0xffdd sci receive vscirx 0xffde:0xffdf sci error vscierr 0xffe0:0xffe1 spi vspi 0xffe2:0xffe3 tpm2 overflow vtpm2ovf 0xffe4:0xffe5 tpm2 channel 1 vtpm2ch1 0xffe6:0xffe7 tpm2 channel 0 vtpm2ch0 0xffe8:0xffe9 tpm1 overflow vtpm1ovf 0xffea:0xffeb reserved ? 0xffec:0xffed reserved ? 0xffee:0xffef tpm1 channel 3 vtpm1ch3 0xfff0:0xfff1 tpm1 channel 2 vtpm1ch2 0xfff2:0xfff3 tpm1 channel 1 vtpm1ch1 0xfff4:0xfff5 tpm1 channel 0 vtpm1ch0 0xfff6:0xfff7 reserved ? 0xfff8:0xfff9 low voltage detect vlvd 0xfffa:0xfffb reserved ? 0xfffc:0xfffd swi vswi 0xfffe:0xffff reset vreset
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 39 4.3 register addresses and bit assignments the registers in the mc9s08el32 series and mc 9s08sl16 series are divided into these groups: ? direct-page registers are located in the first 128 locations in the memory map; these are accessible with efficient direct addressing mode instructions. ? high-page registers are used much less often, so they are located above 0x1800 in the memory map. this leaves more room in the direct page for more frequently used registers and ram. ? the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?0xffbf. nonvolatile regi ster locations include: ? nvprot and nvopt which are loaded into working registers at reset ? an 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with efficient direct addressing mode inst ructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page re gisters and control bits. the direct page registers in table 4-2 can use the more efficient dire ct addressing mode, which requires only the lower byte of the address. b ecause of this, the lower byte of th e address in column one is shown in bold text. in table 4-3 and table 4-4 , the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the right. cells that are not associated with named bits are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 40 freescale semiconductor table 4-2. direct-page register summary (sheet 1 of 3) address register name b i t 7654321b i t 0 0x00 00 ptad ptad7 ptad6 0 0 ptad3 ptad2 ptad1 ptad0 0x00 01 ptadd ptadd7 ptadd6 0 0 ptadd3 ptadd2 ptadd1 ptadd0 0x00 02 ptbd ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 0x00 03 ptbdd ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 0x00 04 ptcd ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 0x00 05 ptcdd ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 0x0006? 0x000d reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 0e acmp1sc acme acbgs acf acie aco acope acmod1 acmod0 0x00 0f acmp2sc acme acbgs acf acie aco acope acmod1 acmod0 0x00 10 adcsc1 coco aien adco adch 0x00 11 adcsc2 adact adtrg acfe acfgt ? ? ? ? 0x00 12 adcrh 0 0 0 0 0 0 adr9 adr8 0x00 13 adcrl adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0x00 14 adccvh 0 0 0 0 0 0 adcv9 adcv8 0x00 15 adccvl adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 0x00 16 adccfg adlpc adiv adlsmp mode adiclk 0x00 17 apctl1 adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 0x00 18 apctl2 adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 0x0019? 0x001f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 20 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 21 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 0x00 22 tpm1cntl b i t 7654321b i t 0 0x00 23 tpm1modh bit 15 14 13 12 11 10 9 bit 8 0x00 24 tpm1modl b i t 7654321b i t 0 0x00 25 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 26 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 27 tpm1c0vl b i t 7654321b i t 0 0x00 28 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 29 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 2a tpm1c1vl b i t 7654321b i t 0 0x00 2b tpm1c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 0x00 2c tpm1c2vh bit 15 14 13 12 11 10 9 bit 8 0x00 2d tpm1c2vl b i t 7654321b i t 0 0x00 2e tpm1c3sc ch3f ch3ie ms3b ms3a els3b els3a 0 0 0x00 2f tpm1c3vh bit 15 14 13 12 11 10 9 bit 8 0x00 30 tpm1c3vl b i t 7654321b i t 0
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 41 0x0031? 0x0037 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 38 scibdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 39 scibdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 3a scic1 loops sciswai rsrc m wake ilt pe pt 0x00 3b scic2 tie tcie rie ilie te re rwu sbk 0x00 3c scis1 tdre tc rdrf idle or nf fe pf 0x00 3d scis2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 3e scic3 r8 t8 txdir txinv orie neie feie peie 0x00 3f scid b i t 7654321b i t 0 0x0040? 0x0047 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 48 icsc1 clks rdiv irefs irclken irefsten 0x00 49 icsc2 bdiv range hgo lp erefs erclken erefsten 0x00 4a icstrm trim 0x00 4b icssc 0 0 0 irefst clkst oscinit ftrim 0x004c ? 0x004f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 50 spic1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 51 spic2 0 0 0 modfen bidiroe 0 spiswai spc0 0x0052 spibr 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 53 spis sprf 0 sptef modf 0 0 0 0 0x0054 reserved 0 0 0 0 0 0 0 0 0x00 55 spid b i t 7654321b i t 0 0x0056? 0x0057 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 58 iica ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 0x00 59 iicf mult icr 0x00 5a iicc1 iicen iicie mst tx txak rsta 0 0 0x00 5b iics tcf iaas busy arbl 0 srw iicif rxak 0x00 5c iicd data 0x00 5d iicc2 gcaen adext 0 0 0 ad10 ad9 ad8 0x005e? 0x005f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 62 tpm2cntl b i t 7654321b i t 0 0x00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 64 tpm2modl b i t 7654321b i t 0 0x00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 table 4-2. direct-page register summary (sheet 2 of 3) address register name b i t 7654321b i t 0
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 42 freescale semiconductor 0x00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 67 tpm2c0vl b i t 7654321b i t 0 0x00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 6a tpm2c1vl b i t 7654321b i t 0 0x006b reserved ? ? ? ? ? ? ? ? 0x00 6c rtcsc rtif rtclks rtie rtcps 0x00 6d rtccnt rtccnt 0x00 6e rtcmod rtcmod 0x006f reserved ? ? ? ? ? ? ? ? 0x00 70 slcc1 0 0 initreq bedd waketx txabrt imsg slcie 0x00 71 slcc2 0r x f ps l c w c m b t m 0slce 0x00 72 slcbth 0 bt14 bt13 bt12 bt11 bt10 bt9 bt8 0x00 73 slcbtl bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 0x00 74 slcs slcact 0 initack 0 0 0 0slcf 0x00 75 slcsv 0 0 i3i2i1i0 0 0 0x00 76 slcdlc txgochkmoddlc5dlc4dlc3dlc2dlc1dlc0 0x00 77 slcid b i t 7654321b i t 0 0x00 78 slcd0 b i t 7654321b i t 0 0x00 79 slcd1 b i t 7654321b i t 0 0x00 7a slcd2 b i t 7654321b i t 0 0x00 7b slcd3 b i t 7654321b i t 0 0x00 7c slcd4 b i t 7654321b i t 0 0x00 7d slcd5 b i t 7654321b i t 0 0x00 7e slcd6 b i t 7654321b i t 0 0x00 7f slcd7 b i t 7654321b i t 0 table 4-2. direct-page register summary (sheet 3 of 3) address register name b i t 7654321b i t 0
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 43 high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the dire ct addressable memory space, starting at 0x1800. table 4-3. high-page register summary (sheet 1 of 2) addressregister namebit 7654321bit 0 0x1800 srs por pin cop ilop ilad 0lvd 0 0x1801 sbdfr 0 0 0 0 0 0 0bdfr 0x1802 sopt1 copt stope scips iicps 0 0 0x1803 sopt2 copclks copw 0 acic t2ch1ps t2ch0ps t1ch1ps t1ch0ps 0x1804 ? 0x1805 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1806 sdidh ? ? ? ? id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 reserved ? ? ? ? ? ? ? ? 0x1809 spmsc1 lv w f lv wac k lv w i e lv d r e lv d s e lv d e 0bgbe 0x180a spmsc2 0 0 lvdv lvwv ppdf ppdack ? ppdc 0x180b? 0x180f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 0x1811 dbgcal bit 7654321bit 0 0x1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 0x1813 dbgcbl bit 7654321bit 0 0x1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 0x1815 dbgfl bit 7654321bit 0 0x1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben 0x1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 0x1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 0x1819? 0x181f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1820 fcdiv divld prdiv8 div 0x1821 fopt keyen fnored epgmod 0 0 0 sec 0x1822 reserved 0 0 0 0 0 0 0 0 0x1823 fcnfg 0 epgsel keyacc 0 0 0 0 0 0x1824 fprot eps fps fpop 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd 0x1827? 0x183f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1840 ptape ptape7 ptape6 0 0 ptape3 ptape2 ptape1 ptape0 0x1841 ptase ptase7 ptase6 0 0 ptase3 ptase2 ptase1 ptase0 0x1842 ptads ptads7 ptads6 0 0 p ta d s 3 p ta d s 2 p ta d s 1 p ta d s 0 0x1843 reserved ? ? ? ? ? ? ? ? 0x1844 ptasc 0 0 0 0 ptaif ptaack ptaie ptamod
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 44 freescale semiconductor 0x1845 ptaps 0 0 0 0 ptaps3 ptaps2 ptaps1 ptaps0 0x1846 ptaes 0 0 0 0 ptaes3 ptaes2 ptaes1 ptaes0 0x1847 reserved ? ? ? ? ? ? ? ? 0x1848 ptbpe ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 0x1849 ptbse ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 0x184a ptbds ptbds7 ptbds6 ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 0x184b reserved ? ? ? ? ? ? ? ? 0x184c ptbsc 0 0 0 0 ptbif ptback ptbie ptbmod 0x184d ptbps 0 0 0 0 ptbps3 ptbps2 ptbps1 ptbps0 0x184e ptbes 0 0 0 0 ptbes3 ptbes2 ptbes1 ptbes0 0x184f reserved ? ? ? ? ? ? ? ? 0x1850 ptcpe ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 0x1851 ptcse ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 0x1852 ptcds ptcds7 ptcds6 ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 0x1853 reserved ? ? ? ? ? ? ? ? 0x1854 ptcsc 0 0 0 0 ptcif ptcack ptcie ptcmod 0x1855 ptcps ptcps7 ptcps6 ptcps5 ptcps4 ptcps3 ptcps2 ptcps1 ptcps0 0x1856 ptces ptces7 ptces6 ptces5 ptces4 ptces3 ptces2 ptces1 ptces0 0x1857 reserved ? ? ? ? ? ? ? ? 0x1858? 0x18ff reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 4-3. high-page register summary (sheet 2 of 2) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 45 nonvolatile flash registers, shown in table 4-4 , are located in the flash memory. these registers include an 8-byte backdoor key, nvbackkey, which can be used to gain access to secure memory resources. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt working registers in the high-page registers to control secu rity and block protection options. provided the key enable (keyen) bit is 1, the 8-by te comparison key can be used to temporarily disengage memory security. this ke y mechanism can be accessed only th rough user code running in secure memory. (a security key cannot be entered directly through ba ckground debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if th e security key is disabled, the only way to disengage security is by mass erasing th e flash if needed (norma lly through the background debug interface) and verifying that flas h is blank. to avoid returning to s ecure mode after the next reset, program the security bits (sec) to the unsecured state (1:0). table 4-4. nonvolatile register summary addressregister namebit 7654321bit 0 0xffae reserved for ftrim storage ? ? ? ? ? ? ?ftrim 0xffaf reserved for icstrm storage trim 0xffb0 ? 0xffb7 nvbackkey 8-byte comparison key 0xffb8 ? 0xffbc reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xffbd nvprot eps fps fpop 0xffbe reserved ? ? ? ? ? ? ? ? 0xffbf nvopt keyen fnored epgmod ? ? ? sec
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 46 freescale semiconductor 4.4 ram the mc9s08el32 series and mc9s08sl16 series incl udes static ram. the locations in ram below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed pr ogram variables in this ar ea of ram is preferred. the ram retains data when the mcu is in low-power wait, stop2, or st op3 mode. at power-on the contents of ram are uninitialized. ram data is unaffected by any rese t provided that the supply voltage does not drop below the minimum value for ram retention (v ram ). for compatibility with m68hc05 mcus, the hcs 08 resets the stack pointer to 0x00ff. in the mc9s08el32 series and mc9s08sl16 series, it is usuall y best to reinitialize the stack pointer to the top of the ram so the direct page ram can be us ed for frequently accessed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your re set initialization routine (where ramlast is equated to the hi ghest address of the ram in the freescale semiconductor-provided equate file). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) when security is enabled, the ram is considered a secure memory resource a nd is not accessible through bdm or through code executing from non-secure memory. see section 4.5.9, ?security ?, for a detailed description of the security feature.
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 47 4.5 flash and eeprom the mc9s08el32 series and mc9s08sl16 series includes flash and eeprom memory intended primarily for program and data stor age. in-circuit programming allows the operating program and data to be loaded into flash and eeprom, respectively, after final assembly of the application product. it is possible to program the arrays through the single-wi re background debug interf ace. because no special voltages are needed for erase an d programming operations, in-application programming is also possible through other software-controlled commu nication paths. for a more detailed discussion of in-circuit and in-application programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor document order number hcs08rmv1/d. 4.5.1 features features of the flash and eeprom memory include: ? array size ? mc9s08el32: 32,768 bytes of flash, 512 bytes of eeprom ? mc9s08el16: 16,384 bytes of flash, 512 bytes of eeprom ? mc9s08sl16: 16,384 bytes of flash, 256 bytes of eeprom ? mc9s08sl8: 8,192 bytes of flash, 256 bytes of eeprom ? sector size: 512 bytes for flash, 8 bytes for eeprom ? single power supply program and erase ? command interface for fast program and erase operation ? up to 100,000 program/erase cycles at typical voltage and temperature ? flexible block protection and vector redirection ? security feature for fl ash, eeprom, and ram 4.5.2 program and erase times before any program or erase comm and can be accepted, the flash a nd eeprom clock divider register (fcdiv) must be written to set the internal clock for the flash and eeprom module to a frequency (f fclk ) between 150 khz and 200 khz (see section 4.5.11.1, ?flash a nd eeprom clock divider register (fcdiv) ?). this register can be written only once, so normally this write is performed during reset initialization. fcdiv cannot be written if the access error flag, fa ccerr in fstat, is set. the user must ensure that faccerr is not set before writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program and erase pulses. an integer number of these timing pulses is used by the command pr ocessor to complete a program or erase command. table 4-5 shows program and erase times . the bus clock fre quency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk =1/f fclk . the times are shown as a number of cycles of fclk and as an ab solute time for the case where t fclk =5 s. program and erase times shown include overhead for the command state machine and enabling and disablin g of program and erase voltages.
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 48 freescale semiconductor 4.5.3 program and erase command execution the fcdiv register must be initialized following a ny reset and any error flag s cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash or eeprom array. the address and data information from this write is latched into th e flash and eeprom interface. this write is a required first step in any command sequence. for erase and blank check commands, the value of the data is not important. for sector erase co mmands, the address can be any address in the 512-byte sector of flash or 8-byte sector of ee prom to be erased. for mass erase and blank check commands, the address can be any addres s in the flash or eeprom memory. flash and eeprom erase independently of each other. note do not program any byte in the flash or eeprom more than once after a successful erase operati on. reprogramming bits in a byte which is already programmed is not allowed without first erasing the sector in which the byte resides or mass erasing the entire flash or eeprom memory. programming without first erasing may disturb data stored in the flash or eeprom. 2. write the command code for th e desired command to fcmd. the six valid commands are blank check (0x05), byte program (0x20), burst program (0x25), sector er ase (0x40), mass erase (0x41), and sector erase abort (0x47). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. aborting a command in this way sets the faccerr acc ess error flag which must be cleared before starting a new command. a strictly monitored procedure must be obeyed or the command will not be accepted. this minimizes the possibility of any unintended changes to the memo ry contents. the command complete flag (fccf) indicates when a command is complete. the comma nd sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a flowchart for executing all of the commands except for burst programming and sect or erase abort. table 4-5. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s burst program 4 20 s 1 1 excluding start/end overhead sector erase 4000 20 ms mass erase 20,000 100 ms sector erase abort 4 20 s 1
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 49 figure 4-2. program and erase flowchart 4.5.4 burst program execution the burst program command is used to program sequential bytes of da ta in less time than would be required using the standard program command. this is possible becaus e the high voltage to the flash array does not need to be disabled between progra m operations. ordinarily, when a program or erase command is issued, an internal ch arge pump associated with the fl ash memory must be enabled to supply high voltage to the array. u pon completion of the command, the ch arge pump is turned off. when a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met: ? the next burst program command has been que ued before the current program operation has completed. ? the next sequential address se lects a byte on the same burst bl ock as the current byte being programmed. a burst block in this flash memory consists of 64 bytes. a new burst block begins at each 64-byte address boundary. start write to flash or eeprom to buffer address and data write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) required only once after reset. program and erase flow
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 50 freescale semiconductor the first byte of a series of sequential bytes being pr ogrammed in burst mode will take the same amount of time to program as a byte progr ammed in standard mode. subsequent bytes will program in the burst program time provided that the conditions above are met. if the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command comple tes, then the charge pump will be disabled and high voltage removed from the array. a flowchart to execute the burst program operation is shown in figure 4-3 . figure 4-3. burst program flowchart 1 0 fcbef ? start write to flash to buffer address and data write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef (2) no yes new burst command ? 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 1 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) required only once after reset. burst program flow
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 51 4.5.5 sector erase abort the sector erase abort operation will terminate the acti ve sector erase operation so that other sectors are available for read and program ope rations without waiting for the sector erase operation to complete. the sector erase abort command write sequence is as follows: 1. write to any flash or eeprom address to start the command write sequence for the sector erase abort command. the address and data written are ignored. 2. write the sector erase abort co mmand, 0x47, to the fcmd register. 3. clear the fcbef flag in the fstat register by wr iting a ?1? to fcbef to launch the sector erase abort command. if the sector erase abort command is launched resulting in the early term ination of an active sector erase operation, the faccerr flag will se t once the operation completes as i ndicated by the fccf flag being set. the faccerr flag sets to inform the user that the flash se ctor may not be full y erased and a new sector erase command must be launched before pr ogramming any location in that specific sector. if the sector erase abort command is launched but the active sector erase operation completes normally, the faccerr flag will not se t upon completion of the ope ration as indicated by the fccf flag being set. therefore, if the faccerr flag is not set after the sector erase abort command has completed, a sector being erased when the abort command was launched will be fully erased. a flowchart to execute the sector erase abort operation is shown in figure 4-4 . figure 4-4. sector erase abort flowchart start write 0x47 to fcmd write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf ? sector erase aborted (2) wait at least four bus cycles 0 1 fccf ? write to flash to buffer address and data faccerr ? 0 1 sector erase completed before checking fcbef or fccf. sector erase abort flow
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 52 freescale semiconductor note the fcbef flag will not set after launching the sector erase abort command. if an attempt is made to start a new command write sequence with a sector erase abort operation act ive, the faccerr flag in the fstat register will be set. a new comma nd write sequence may be started after clearing the accerr flag, if set. note the sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4.5.6 access errors an access error occurs whenever the co mmand execution protocol is violated. any of the following specif ic actions will cause the access error fl ag (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. ? writing to a flash address before the internal flash and eeprom clock frequency has been set by writing to the fcdiv register. ? writing to a flash address while fcbef is not set. (a new comm and cannot be st arted until the command buffer is empty.) ? writing a second time to a flash address before launching the previous command. (there is only one write to flash for every command.) ? writing a second time to fcmd before launching the previous command. (there is only one write to fcmd for every command.) ? writing to any flash control register other than fcmd after writing to a flash address. ? writing any command code other than th e six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or 0x47) to fcmd. ? writing any flash control register other than to write to fsta t (to clear fcbef and launch the command) after writing the command to fcmd. ? the mcu enters stop mode while a program or er ase command is in progress. (the command is aborted.) ? writing the byte program, burst program, sector erase or sector erase a bort command code (0x20, 0x25, 0x40, or 0x47) with a background debug command while the mcu is secured. (the background debug controller can do blank check and mass erase commands only when the mcu is secure.) ? writing 0 to fcbef to cancel a partial command.
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 53 4.5.7 block protection the block protection featur e prevents the protected region of fl ash or eeprom from program or erase changes. block protection is controlled through th e flash and eeprom protection register (fprot). the eps bits determine the protec ted region of eeprom and the fps bits determine the protected region of flash. see section 4.5.11.4, ?flash and eeprom prot ection register (fprot and nvprot) ?. after exit from reset, fprot is lo aded with the contents of the nvprot location, which is in the nonvolatile register block of the flash memory. fprot cannot be changed directly from application software so a runaway program cannot alter the block protection setti ngs. because nvprot is within the last sector of flash, if any amount of memory is protected, nvprot is itself protected and cannot be altered (intentionally or unintenti onally) by the application software. fprot can be written through background debug commands, which provides a way to erase and reprogram protected flash memory. one use for block protection is to block protect an area of flash me mory for a bootloader program. this bootloader program can call a routine outside of flas h that can sector erase the rest of the flash memory and reprogram it. the bootload er is protected even if mcu power is lost during an erase and reprogram operation. 4.5.8 vector redirection whenever any flash is block protected, the reset and interrupt vectors will be protected. vector redirection allows users to modify interrupt vector information wit hout unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to 0. for re direction to occur, at least some portion of the fl ash memory must be block protected by programming the nvprot register located at address 0xffbd. all interrupt vectors (memory locations 0xffc0?0xfffd) are redirect ed, though the reset vect or (0xfffe:0xffff) is not. for example, if 1024 bytes of flas h are protected, the pr otected address region is from 0xfc00 through 0xffff. the interrupt vectors (0xffc0?0xfffd) are redirected to the locations 0xfbc0?0xfbfd. if vector redirection is enab led and an interrupt occurs, the values in the locations 0xfbe0:0xfbe1 are used for the vector instead of the values in the locations 0xffe0:0xffe1. this allows the user to reprogram the unprotected portion of the flash with new program code including new interrupt vector values while leaving the protected area, which include s the default vector locations, unchanged. 4.5.9 security the mc9s08el32 series and mc9s08sl16 series include s circuitry to prevent unauthorized access to the contents of flash, eeprom, and ram memory. when security is engaged, flash, eeprom, and ram are considered secure resources. direct-page registers, high-pa ge registers, and the background debug controller are considered unsecured resources. programs executi ng within secure memory have normal access to any mcu me mory locations and resources. attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). security is engaged or disengaged ba sed on the state of two register bits (sec[1:0]) in the fopt register. during reset, the contents of th e nonvolatile location nvopt are copi ed from flash into the working
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 54 freescale semiconductor fopt register in high-page regist er space. a user engages securi ty by programming the nvopt location, which can be performed at the same time the flash memory is programmed. the 1:0 state disengages security; the other three combinations engage secu rity. notice the erased state (1:1) makes the mcu secure. during development, whenever the flash is erased, it is good practice to immediately program the sec0 bit to 0 in nvopt so sec = 1:0. this would allow the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can be used for background memo ry access commands of unsecured resources. a user can choose to allow or disallow a securi ty unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile ke yen bit in nvopt/fopt is 0, the b ackdoor key is disabled and there is no way to disengage security without completely erasing all flash locations. if keyen is 1, a secure user program can temporar ily disengage security by: 1. writing 1 to keyacc in the fcnfg register. th is makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbackkey+7) as values to be compared against the key rather than as the first step in a flash pr ogram or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be performed in order st arting with the value for nvbackkey and ending with nvbackkey+7. sthx must not be used fo r these writes because these writes cannot be performed on adjacent bus cycles. user software normally would ge t the key codes from outside the mcu system through a communication interface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was written matches the key stored in the flash locations, sec bits are auto matically changed to 1:0 and security will be disengaged until the next reset. the security key can be written only from secure memory (either ram, eeprom, or flash), so it cannot be entered through background commands without the cooperati on of a secure user program. the backdoor comparison key (nvbackkey through nvbackkey+7) is locate d in flash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other flash memory lo cation. the nonvolatile registers ar e in the same 768-byte block of flash as the reset and inte rrupt vectors, so block protecting that space also block protects the backdoor comparison key. block protec ts cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechan ism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through th e background debug interfac e by taking these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec = 1:0.
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 55 4.5.10 eeprom mapping only half of the eeprom is in the memory map. the epgsel bit in fcnfg regi ster selects which half of the array can be accessed in foreground while the other half can not be accessed in background. there are two mapping mode options that can be selected to configure the 8-byte eeprom sectors: 4-byte mode and 8-byte mode. each mode is selected by the epgmod bit in the fopt register. in 4-byte sector mode (epgmod = 0) , each 8-byte sector splits four bytes on foreground and four bytes on background but on the same addresses. the epgs el bit selects which four bytes can be accessed. during a sector erase, the entire 8- byte sector (four bytes in foregr ound and four bytes in background) is erased. in 8-byte sector mode (epgmod = 1), each entire 8-byte sector is in a single page. the epgsel bit selects which sectors are on background. during a sector erase, the entire 8-byte sector in foreground is erased. 4.5.11 flash and eeprom registers and control bits the flash and eeprom module has seven 8-bit regi sters in the high-page register space and three locations in the nonvolatile register space in flash memory. two of those locations are copied into two corresponding high-page control registers at reset. there is also an 8-byte comparison key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignments for all flash and eeprom registers. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or h eader file normally is used to translate these names into the appropriate absolute addresses. 4.5.11.1 flash and eeprom clock divider register (fcdiv) before any erase or progra mming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. bit 7 is a read-only flag and bits 0 to 6 may be read at any time but can be written only one time after reset. 76543210 rdivld prdiv8 div w r e s e t00000000 = unimplemented or reserved figure 4-5. flash and eeprom clock divider register (fcdiv)
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 56 freescale semiconductor if prdiv8 = 0 ? f fclk = f bus (div + 1) eqn. 4-1 if prdiv8 = 1 ? f fclk = f bus (8 (div + 1)) eqn. 4-2 table 4-7 shows the appropriate values for prdi v8 and div for selected bus frequencies. table 4-6. fcdiv regist er field descriptions field description 7 divld divisor loaded status flag ? when set, this read-only status flag indicates that the fcdiv register has been written since reset. reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been writ ten since reset; erase and program ope rations disabled for flash and eeprom. 1 fcdiv has been written since reset; erase and program operations enabled for flash and eeprom. 6 prdiv8 prescale (divide) flash and eeprom clock by 8 0 clock input to the flash and eeprom clock divider is the bus rate clock. 1 clock input to the flash and eeprom clock divider is the bus rate clock divided by 8. 5:0 div divisor for flash and eeprom clock divider ? the flash and eeprom clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div field plus one. the resulting frequency of the internal fl ash and eeprom clock must fall within the range of 200 khz to 150 khz for proper flash operations. program/erase timing pulses are o ne cycle of this internal flash and eeprom clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. see equation 4-1 and equation 4-2 . table 4-7. flash and eeprom clock divider settings f bus prdiv8 (binary) div (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 57 4.5.11.2 flash and eeprom opti ons register (fopt and nvopt) during reset, the contents of th e nonvolatile location nvopt are copied from flash into fopt. to change the value in this register, erase and repr ogram the nvopt location in flash memory as usual and then issue a new mcu reset. 76543210 r keyen fnored epgmod 0 0 0 sec w r e s e tfff000ff = unimplemented or reserved figure 4-6. flash and eeprom options register (fopt) table 4-8. fopt register field descriptions field description 7 keyen backdoor key mechanism enable ? when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) firmware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to section 4.5.9, ?security .? 0 no backdoor key access allowed. 1 if user firmware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is te mporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ? when this bit is 1, then vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled. 5 epgmod eeprom sector mode ? when this bit is 0, each sector is split into two pages (4-byte mode). when this bit is 1, each sector is in a single page (8-byte mode). 0 half of each eeprom sector is in page 0 and the other half is in page 1. 1 each sector is in a single page. 1:0 sec security state code ? this 2-bit field determines the security state of the mcu as shown in ta bl e 4 - 9 . when the mcu is secure, the c ontents of ram, eeprom and flash memory cannot be accessed by instructions from any unsecured source including the background deb ug interface. sec changes to 1:0 after successful backdoor key entry or a successful blank check of flash. for more detailed information about security, refer to section 4.5.9, ?security .? table 4-9. security states 1 1 sec changes to 1:0 after successful backdoor key entry or a successful blank check of flash. sec[1:0] description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 58 freescale semiconductor 4.5.11.3 flash and eeprom configuration register (fcnfg) 76543210 r0 epgsel keyacc 00000 w r e s e t00000000 = unimplemented or reserved figure 4-7. flash and eeprom conf iguration register (fcnfg) table 4-10. fcnfg register field descriptions field description 6 epgsel eeprom page select ? this bit selects which eeprom page is accessed in the memory map. 0 page 0 is in foreground of memory map. page 1 is in background and can not be accessed. 1 page 1 is in foreground of memory map. page 0 is in background and can not be accessed. 5 keyacc enable writing of access key ? this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to section 4.5.9, ?security .? 0 writes to 0xffb0?0xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?0xffb7) are interpreted as comparison key writes.
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 59 4.5.11.4 flash and eeprom protecti on register (fprot and nvprot) fprot register defines which flash and eeprom s ectors are protected against program and erase operations. during the reset sequence, the fprot register is loaded from the nonvolatile location nvprot. to change the protection that will be loaded during th e reset sequence, the sector containing nvprot must be unprotected and erased, then nvprot can be reprogrammed. fprot bits are readable at any time and writable as long as the size of the protected region is being increased. any write to fprot that attempts to decrea se the size of the protecte d region will be ignored. trying to alter data in any protected area will result in a protection violation error and the fpviol flag will be set in the fstat register . mass erase is not possible if a ny one of the sectors is protected. figure 4-8. flash and eeprom protection register (fprot) 76543210 r eps fps fpop w r e s e tffffffff table 4-11. fprot register field descriptions field description 7:6 eps eeprom protect select bits ? this 2-bit field determines the protected eeprom locations that cannot be erased or programmed. see ta bl e 4 - 1 2 . 5:1 fps flash protect select bits ? this 5-bit field determines the protec ted flash locations that cannot be erased or programmed. see ta bl e 4 - 1 3 . 0 fpop flash protect open bit ? this bit determines the protected flash locations that cannot be erased or programmed. see ta bl e 4 - 1 3 . table 4-12. eeprom block protection eps address area protected memory size protected (bytes) number of sectors protected 0x3 n/a 0 0 0x2 0x17f8 - 0x17ff 16 2 0x1 0x17f0 - 0x17ff 32 4 0x0 0x17e0?0x17ff 64 8
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 60 freescale semiconductor table 4-13. flash block protection fps fpopen address area protected memory size protected (bytes) number of sectors protected 0x1f 1 n/a 0 0 0x1e 0xfc00?0xffff 1k 2 0x1d 0xf800?0xffff 2k 4 0x1c 0xf400?0xffff 3k 6 0x1b 0xf000?0xffff 4k 8 0x1a 0xec00?0xffff 5k 10 0x19 0xe800?0xffff 6k 12 0x18 0xe400?0xffff 7k 14 0x17 0xe000?0xffff 8k 16 ... ... ... 18 0x07 0xa000?0xffff 24k 48 0x06 0x9c00?0xffff 25k 50 0x05 0x9800?0xffff 26k 52 0x04 0x9400?0xffff 27k 54 0x03 0x9000?0xffff 28k 56 0x02 0x8c00?0xffff 29k 58 0x01 0x8800?0xffff 30k 60 0x00 0x8400?0xffff 31k 62 n/a 0 0x8000?0xffff 32k 64
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 61 4.5.11.5 flash and eeprom status register (fstat) 76543210 r fcbef fccf fpviol faccerr 0fblank0 0 w r e s e t11000000 = unimplemented or reserved figure 4-9. flash and eeprom status register (fstat) table 4-14. fstat regist er field descriptions field description 7 fcbef command buffer empty flag ? the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command can be written to the command buffer. 6 fccf command complete flag ? fccf is set automatical ly when the command buffer is empty and no command is being processed. fccf is cleared automatically when a new command is started (by writing 1 to fcbef to register a command). writing to f ccf has no meaning or effect. 0 command in progress 1 all commands complete 5 fpviol protection violation flag ? fpviol is set automatically when a command is written that attempts to erase or program a location in a protected block (the erroneous comma nd is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location. 4 faccerr access error flag ? faccerr is set automatically when the pr oper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or eras e operation is attempted befo re the fcdiv register has been initialized, or if the mcu enters stop while a comm and was in progress. for a more detailed discussion of the exact actions that are considered access errors, see section 4.5.6, ?access errors .? faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 0 no access error. 1 an access error has occurred. 2 fblank verified as all blank (erased) flag ? fblank is set automatically at t he conclusion of a blank check command if the entire flash or eeprom array was verified to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fblank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash or eeprom array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash or eeprom array is completely erased (all 0xffff).
chapter 4 memory mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 62 freescale semiconductor 4.5.11.6 flash and eeprom command register (fcmd) only six command codes ar e recognized in normal user modes as shown in table 4-15 . all other command codes are illegal and generate an access error. refer to section 4.5.3, ?program and erase command execution ,? for a detailed discussion of flash and eeprom programming and erase operations. it is not necessary to perform a blank check comma nd after a mass erase operation. only blank check is required as part of the se curity unlocking mechanism. 76543210 r00000000 wfcmd reset00000000 = unimplemented or reserved figure 4-10. flash and eeprom command register (fcmd) table 4-15. flash and eeprom commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog burst program 0x25 mburstprog sector erase 0x40 msectorerase mass erase 0x41 mmasserase sector erase abort 0x47 meraseabort
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 63 chapter 5 resets, interrupts, and general system control 5.1 introduction this section discusses basic reset a nd interrupt mechanisms and the various sources of reset and interrupt in the mc9s08el32 series and mc9s08sl16 series. some interrupt sources from peripheral modules are discussed in greater detail with in other sections of this data sheet. this section gathers basic information about all reset and interr upt sources in one pla ce for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog are not part of on-chip peripheral systems with their own chapters. 5.2 features reset and interrupt features include: ? multiple sources of reset for flexible sy stem configuration an d reliable operation ? reset status register (srs) to indicate source of most recent reset ? separate interrupt vector for each m odule (reduces polling overhead) (see table 5-2 ) 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers ar e forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral m odules are disabled and i/o pins are initially configured as general-purpose hi gh-impedance inputs with pull-up de vices disabled. the i bit in the condition code register (ccr) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system c ontrol settings. sp is forced to 0x00ff at reset. the mc9s08el32 series and mc9s08sl16 series has eight sources for reset: ? power-on reset (por) ? external pin reset (pin) ? low-voltage detect (lvd) ? computer operating properly (cop) timer ? illegal opcode detect (ilop) ? illegal address detect (ilad) ? background debug forced reset each of these sources, with the ex ception of the background debug forced reset, has an associated bit in the system reset status register (srs).
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 64 freescale semiconductor 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset wh en the application software fails to execute as expected. to prevent a system reset from the cop time r (when it is enabled), ap plication software must reset the cop counter periodically. if the application pr ogram gets lost and fails to reset the cop counter before it times out, a sy stem reset is generated to force the system back to a known starting point. after any reset, the cop watchdog is enabled (see section 5.7.3, ?system options register 1 (sopt1) ,? for additional information). if the cop watchdog is not used in an a pplication, it can be disabled by clearing copt bits in sopt1. the cop counter is reset by writi ng 0x0055 and 0x00aa (in this order) to the address of srs during the selected timeout period. writes do not affect the data in the read-only srs. as soon as the write sequence is done, the cop timeout pe riod is restarted. if the pr ogram fails to do this duri ng the time-out period, the mcu will reset. also, if any value other than 0x0055 or 0x00aa is written to srs, the mcu is immediately reset. the copclks bit in sopt2 (see section 5.7.4, ?system options register 2 (sopt2) ,? for additional information) selects the clock sour ce used for the cop timer. the cloc k source options are either the bus clock or an internal 1-khz clock source. with each clock source, th ere are three asso ciated time-outs controlled by the copt bits in sopt1. table 5-1 summaries the control func tions of the copclks and copt bits. the cop watchdog defaults to operation from the 1-khz cl ock source and the longest time-out (2 10 cycles). when the bus clock source is selected, windowed cop operation is available by setting copw in the sopt2 register. in this mode, writes to the srs register to clear the co p timer must occur in the last 25% of the selected timeout period. a premature write immediately resets the mcu. when the 1-khz clock source is selected, windowed cop operation is not available. table 5-1. cop configuration options control bits clock source cop overflow count copclks copt[1:0] n/a 0:0 n/a cop is disabled 00 : 1 1 khz 2 5 cycles (32 ms 1 ) 1 values are shown in this column based on t rti =1ms. see t rti in the appendix section a.12.1, ?control timing ,? for the tolerance of this value. 01 : 0 1 khz 2 8 cycles (256 ms 1 ) 01 : 1 1 khz 2 10 cycles (1.024 s 1 ) 10 : 1 bus 2 13 cycles 11 : 0 bus 2 16 cycles 11 : 1 bus 2 18 cycles
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 65 the cop counter is initialized by the first writes to the sopt1 and sopt2 registers after any system reset. subsequent writes to sopt 1 and sopt2 have no effect on cop operation. even if the application will use the reset default settings of copt , copclks, and copw bits, the user should write to the write-once sopt1 and sopt2 registers during reset initialization to lock in the sett ings. this will pr event accidental changes if the application program gets lost. the write to srs that services (clear s) the cop counter should not be plac ed in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. if the bus clock source is selected, the cop coun ter does not increment while the mcu is in background debug mode or while the system is in stop mode . the cop counter resumes when the mcu exits background debug mode or stop mode. if the 1-khz clock source is sele cted, the cop counter is re-initial ized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode. 5.5 interrupts interrupts provide a way to save the current cpu status and registers, ex ecute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caus ed by hardware events such as an edge on an external in terrupt pin or a timer-ove rflow event. the debug module can also generate an swi under certain circumstances. if an event occurs in an enabled interrupt source, an associated read-only status flag will become set. the cpu will not respond unless the local in terrupt enable is a 1 to enable th e interrupt and the i bit in the ccr is 0 to allow interrupts. the global interrupt mask (i bit) in the ccr is initially set after reset which prevents all maskable interrupt sources. the user pr ogram initializes the stack pointer and performs other system setup before clearing the i bit to allow the cpu to respond to interrupts. when the cpu receives a qua lified interrupt request, it completes the current in struction before responding to the interrupt. the interrupt sequence obeys the sa me cycle-by-cycle sequence as the swi instruction and consists of: ? saving the cpu registers on the stack ? setting the i bit in the ccr to mask further interrupts ? fetching the interrupt vector for the highest-priority interrupt that is currently pending ? filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restor ed from the value stacked on entry to the isr. in rare cases, the i bit can be cleared inside an isr (after clearing the stat us flag that generated the interrupt) so that other interrupts can be serviced without waiting for the fi rst service routine to finish. this practice is not
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 66 freescale semiconductor recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. the interrupt service routine ends wi th a return-from-interrupt (rti) in struction which restores the ccr, a, x, and pc registers to their pr e-interrupt values by read ing the previously save d information from the stack. note for compatibility with m68hc08 devices, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the inte rrupt service routine (isr) and restore it immediately before the rti that is used to return from the isr. if more than one interrupt is pending when the i bit is cleare d, the highest priority s ource is serviced first (see table 5-2 ). 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next av ailable byte location on the stack. the curr ent values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next avai lable location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu fills the instruction pipeline by reading th ree bytes of program information, starting from the pc address recovered from the stack. condition code register accumulator index register (low byte x) program counter high * high byte (h) of index register is not automatically stacked. * program counter low 2 2 2 2 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 67 the status flag corresponding to th e interrupt source must be acknow ledged (cleared) before returning from the isr. typically, the flag is cleared at the beginning of the isr so that if another interrupt is generated by this same source , it will be registered so it can be serviced after completion of the current isr. 5.5.2 interrupt vectors, sources, and local masks table 5-2 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byt e of the address for the interrupt service routine is located at the first address in the vector address column, and the lo w-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated flag bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will finish the current inst ruction; stack the pcl, pch, x, a, and ccr cpu registers; set the i bit; and then fetch the interrupt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine.
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 68 freescale semiconductor 5.6 low-voltage detect (lvd) system the mc9s08el32 series and mc9s08sl16 series incl udes a system to protect against low voltage conditions in order to protect memory contents a nd control mcu system stat es during supply voltage variations. the system is comprised of a power-on rese t (por) circuit and a lvd ci rcuit with trip voltages table 5-2. vector summary vector priority vector number address (high/low) vector name module source enable description lowest highest 31 0xffc0/0xffc1 vacmp2 acmp2 acf acie analog comparator 2 30 0xffc2/0xffc3 vacmp1 acmp1 acf acie analog comparator 1 29 0xffc4/0xffc5 ? ? ? ? ? 28 0xffc6/0xffc7 ? ? ? ? ? 27 0xffc8/0xffc9 ? ? ? ? ? 26 0xffca/0xffcb ? ? ? ? ? 25 0xffcc/0xffcd vrtc rtc rtif rtie real-time interrupt 24 0xffce/0xffcf viic iic iicis iicie iic control 23 0xffd0/0xffd1 vadc adc coco aien adc 22 0xffd2/0xffd3 vportc port c ptcif ptcie port c pins 21 0xffd4/0xffd5 vportb port b ptbif ptbie port b pins 20 0xffd6/0xffd7 vporta port a ptaif ptaie port a pins 19 0xffd8/0xffd9 vslic slic slcf slcie slic 18 0xffda/0xffdb vscitx sci tdre, tc tie, tcie sci transmit 17 0xffdc/0xffdd vscirx sci idle, lbkdif, rdrf, rxedgif ilie, lbkdie, rie, rxedgie sci receive 16 0xffde/0xffdf vscierr sci or, nf, fe, pf orie, nfie, feie, pfie sci error 15 0xffe0/0xffe1 vspi spi spif, modf, sptef spie, spie, sptie spi 14 0xffe2/0xffe3 vtpm2ovf tpm2 tof toie tpm2 overflow 13 0xffe4/0xffe5 vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 12 0xffe6/0xffe7 vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 11 0xffe8/0xffe9 vtpm1ovf tpm1 tof toie tpm1 overflow 10 0xffea/0xffeb ? ? ? ? ? 9 0xffec/0xffed ? ? ? ? ? 8 0xffee/0xffef vtpm1ch3 tpm1 ch3f ch3ie tpm1 channel 3 7 0xfff0/0xfff1 vtpm1ch2 tpm1 ch2f ch2ie tpm1 channel 2 6 0xfff2/0xfff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 5 0xfff4/0xfff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 4 0xfff6/0xfff7 ? ? ? ? ? 3 0xfff8/0xfff9 vlvd system control lv w f lv w i e l ow - vo l t a g e wa r n i n g 2 0xfffa/0xfffb ? ? ? ? ? 1 0xfffc/0xfffd vswi core swi in struction ? software interrupt 0 0xfffe/0xffff vreset system control cop, lv d, reset pin, illegal opcode, illegal address copt lv d r e ? ? ? watchdog timer low-voltage detect external pin illegal opcode illegal address
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 69 for warning and detection. the lvd circuit is enab led when lvde in spmsc1 is set to 1. the lvd is disabled upon entering any of the stop modes unless lvdse is set in spmsc1. if lvdse and lvde are both set, then the mcu cannot enter stop2, and the current consumption in stop3 with the lvd enabled will be higher. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply volta ge drops below the power-on reset rearm voltage level, v por , the por circuit will cause a reset c ondition. as the supply voltage rises, the lvd circuit will hold the mcu in reset until the s upply has risen above the lo w voltage detection low threshold, v lvdl . both the por bit and the lvd bi t in srs are set following a por. 5.6.2 low-voltage detection (lvd) reset operation the lvd can be configured to generate a reset upon detection of a low vol tage condition by setting lvdre to 1. the low voltage detectio n threshold is determined by the lvdv bit. after an lvd reset has occurred, the lvd system will hold the mcu in rese t until the supply voltage has risen above the low voltage detection threshold. the lvd bit in the srs regi ster is set following either an lvd reset or por. 5.6.3 low-voltage warning (lvw) interrupt operation the lvd system has a low voltage warning flag to indicate to the user that the supply voltage is approaching the low voltage condition. when a low voltage warning condition is detected and is configured for interrupt operation (lvwie set to 1), lvwf in spmsc1 will be set and an lvw interrupt request will occur.
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 70 freescale semiconductor 5.7 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space a nd eight 8-bit registers in th e high-page register space are related to reset and interrupt systems. refer to table 4-2 and table 4-3 in chapter 4, ?memory ,? of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. some control bits in the sopt1 and spmsc2 registers are related to mode s of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in chapter 3, ?modes of operation .?
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 71 5.7.1 system reset status register (srs) this high page register incl udes read-only status flags to indicate th e source of the most recent reset. when a debug host forces reset by wr iting 1 to bdfr in the sbdf r register, none of the st atus bits in srs will be set. writing any value to this register address causes a cop reset wh en the cop is enabled except the values 0x55 and 0xaa. writing a 0x55-0xaa sequence to this address clears the cop watchdog timer without affecting the contents of th is register. the reset state of these bits depends on what caused the mcu to reset. figure 5-2. system reset status (srs) 76543210 r por pin cop ilop ilad 0 lvd 0 w writing 0x55, 0xaa to srs address clears cop watchdog timer. por: 10000010 lv d : 00000010 any other reset: 0note (1) 1 any of these reset sources that are active at the time of re set entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. note (1) note (1) note (1) 000 table 5-3. srs register field descriptions field description 7 por power-on reset ? reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvd) status bit is also set to indicate that the reset occurred while the internal supply was below the lvd threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ? reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. 5 cop computer operating properly (cop) watchdog ? reset was caused by the cop watchdog timer timing out. this reset source can be blocked by cope = 0. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode ? reset was caused by an attempt to execut e an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt regi ster. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode.
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 72 freescale semiconductor 5.7.2 system background debug force reset register (sbdfr) this high page register contains a single write-only control bit. a serial background command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. figure 5-3. system background debug force reset register (sbdfr) 3 ilad illegal address ? reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 reset not caused by an illegal address 1 reset caused by an illegal address 1 lv d low voltage detect ? if the lvdre bit is set and the supply drops below the lvd trip voltage, an lvd reset will occur. this bit is also set by por. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background debug commands, not from user programs. r e s e t :00000000 = unimplemented or reserved table 5-4. sbdfr register field descriptions field description 0 bdfr background debug force reset ? a serial background command such as write_byte can be used to allow an external debug host to force a target system reset. writing 1 to this bit forc es an mcu reset. this bit cannot be written from a user program. table 5-3. srs register field descriptions field description
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 73 5.7.3 system options register 1 (sopt1) this high page register is a write-once register so only the first write after reset is honored. it can be read at any time. any subsequent attempt to write to so pt1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt1 should be writte n during the user?s reset initialization program to set the desi red controls even if the desired se ttings are the same as the reset settings. 76543210 r copt stope scips iicps 00 w r e s e t :11000000 = unimplemented or reserved figure 5-4. system options register 1 (sopt1) table 5-5. sopt1 register field descriptions field description 7:6 copt[1:0] cop watchdog timeout ? these write-once bits select the tim eout period of the cop. copt along with copclks in sopt2 defines t he cop timeout period. see ta b l e 5 - 1 . 5 stope stop mode enable ? this write-once bit is used to enable stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled. 1 stop mode enabled. 4 scips sci pin select ? this write-once bit selects the location of the rxd and txd pins of the sci module. 0 rxd on ptb0, txd on ptb1. 1 rxd on pta2, txd on pta3. 3:2 iicps iic pin select ? these write-once bits select the location of the scl and sda pins of the iic module. 00 sda on pta2, scl on pta3. 01 sda on ptb6, scl on ptb7. 1x sda on ptb2, scl on ptb3.
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 74 freescale semiconductor 5.7.4 system options register 2 (sopt2) this high page register contains bits to configure mcu specific f eatures on the mc9s08el32 series and mc9s08sl16 series devices. 76543210 r copclks 1 1 this bit can be written only one time after reset. additional writes are ignored. copw 1 0 acic 1 t2ch1ps 1 t2ch0ps 1 t1ch1ps 1 t1ch0ps 1 w r e s e t :00000000 = unimplemented or reserved figure 5-5. system options register 2 (sopt2) table 5-6. sopt2 register field descriptions field description 7 copclks cop watchdog clock select ? this write-once bit selects the clock source of the cop watchdog. 0 internal 1-khz clock is source to cop. 1 bus clock is source to cop. 6 copw cop window ? this write-once bit selects the cop operatio n mode. when set, the 0x55-0xaa write sequence to the srs register must occur in the last 25% of the se lected period. any write to the srs register during the first 75% of the selected period will reset the mcu. 0 normal cop operation 1 window cop operation 4 acic analog comparator to input capture enable ? this write-once bit connects the output of acmp1 to tpm1 input channel 0. 0 acmp1 output not connected to tpm1 input channel 0. 1 acmp1 output connected to tpm1 input channel 0. 3 t2ch1ps tpm2ch1 pin select ? this write-once bit selects the location of the tpm2ch1 pin of the tpm2 module. 0 tpm2ch1 on ptb4. 1 tpm2ch1 on pta7. 2 t2ch0ps tpm2ch0 pin select ? this write-once bit selects the location of the tpm2ch0 pin of the tpm2 module. 0 tpm2ch0 on pta1. 1 tpm2ch0 on pta6. 1 t1ch1ps tpm1ch1 pin select ? this write-once bit selects the location of the tpm1ch1 pin of the tpm1 module. 0 tpm1ch1 on ptb5. 1 tpm1ch1 on ptc1. 0 t1ch0ps tpm1ch0 pin select ? this write-once bit selects the location of the tpm1ch0 pin of the tpm1 module. 0 tpm1ch0 on pta0. 1 tpm1ch0 on ptc0.
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 75 5.7.5 system device identificati on register (sdidh, sdidl) these high page read-only registers are included so host development systems can identify the hcs08 derivative and revision number. this allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target mcu. figure 5-6. system device identification register ? high (sdidh) 76543210 r id11 id10 id9 id8 w reset: 0 1 1 the revision number that is hard coded into these bits reflects the current silicon revision level. 0 1 0 1 0 1 0000 = unimplemented or reserved table 5-7. sdidh register field descriptions field description 3:0 id[11:8] part identification number ? each derivative in the hcs08 family has a unique identification number. the mc9s08el32 is hard coded to the value 0x013. see also id bits in ta bl e 5 - 8 . 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w r e s e t :00010011 = unimplemented or reserved figure 5-7. system device identification register ? low (sdidl) table 5-8. sdidl register field descriptions field description 7:0 id[7:0] part identification number ? each derivative in the hcs08 family has a unique identification number. the mc9s08el32 is hard coded to the value 0x013. see also id bits in ta bl e 5 - 7 .
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 76 freescale semiconductor 5.7.6 system power management st atus and control 1 register (spmsc1) this high page register contains st atus and control bits to support the low voltage detect function, and to enable the bandgap voltage refe rence for use by the adc module. figure 5-8. system power management status and control 1 register (spmsc1) 76543210 rlvwf 1 1 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lv w 0 lv w i e lv d r e 2 2 this bit can be written only one time after reset. additional writes are ignored. lv d s e 2 lv d e 2 0 bgbe w lv wac k r e s e t :00011100 = unimplemented or reserved table 5-9. spmsc1 register field descriptions field description 7 lv w f low-voltage warning flag ? the lvwf bit indicates the low voltage warning status. 0 low voltage warning is not present. 1 low voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge ? the lvwf bit indicates the low voltage warning status.writing a 1 to lvwack clears lvwf to a 0 if a low voltage warning is not present. 5 lv w i e low-voltage warning interrupt enable ? this bit enables hardware interrupt requests for lvwf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvwf = 1. 4 lvdre low-voltage detect reset enable ? this write-once bit enables lv d events to generate a hardware reset (provided lvde = 1). 0 lvd events do not generate hardware resets. 1 force an mcu reset when an enabled low-voltage detect event occurs. 3 lv d s e low-voltage detect stop enable ? provided lvde = 1, this read/writ e bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lv d e low-voltage detect enable ? this write-once bit enables low-volt age detect logic and qualifies the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled. 0 bgbe bandgap buffer enable ? this bit enables an internal buffer for the bandgap voltage reference for use by the adc module on one of its internal channels. 0 bandgap buffer disabled. 1 bandgap buffer enabled.
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 77 5.7.7 system power management st atus and control 2 register (spmsc2) this register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the mcu. figure 5-9. system power management status and control 2 register (spmsc2) 76543 210 r0 0 lv dv 1 1 this bit can be written only one time after power-on reset. additional writes are ignored. lv w v ppdf 0 0 ppdc 2 2 this bit can be written only one time after reset. additional writes are ignored. w ppdack p o w e r - o n r e s e t :00000 000 l v d r e s e t :00uu0 000 any other reset: 0 0 u u 0 0 0 0 = unimplemented or reserved u = unaffected by reset table 5-10. spmsc2 regist er field descriptions field description 5 lv dv low-voltage detect voltage select ? this write-once bit selects the low voltage detect (lvd) trip point setting. it also selects the warning voltage range. see ta b l e 5 - 1 1 . 4 lv w v low-voltage warning voltage select ? this bit selects the low voltage warning (lvw) trip point voltage. see ta b l e 5 - 1 1 . 3 ppdf partial power down flag ? this read-only status bit indicates t hat the mcu has recovered from stop2 mode. 0 mcu has not recovered from stop2 mode. 1 mcu recovered from stop2 mode. 2 ppdack partial power down acknowledge ? writing a 1 to ppdack clears the ppdf bit 0 ppdc partial power down control ? this write-once bit controls whet her stop2 or stop3 mode is selected. 0 stop3 mode enabled. 1 stop2, partial power down, mode enabled. table 5-11. lvd and lvw trip point typical values 1 1 see electrical characteristics appendix for minimum and maximum values. lvdv:lvwv lvw trip point lvd trip point 0:0 v lv w 0 = 2.74 v v lv d 0 = 2.56 v 0:1 v lv w 1 = 2.92 v 1:0 v lv w 2 = 4.3 v v lv d 1 = 4.0 v 1:1 v lv w 3 = 4.6 v
chapter 5 resets, interrupts, and general system control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 78 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 79 chapter 6 parallel input/output control this section explains software c ontrols related to parallel input/ output (i/o) and pin control. the mc9s08el32 has three parallel i/o ports which include a total of 22 i/o pins. see chapter 2, ?pins and connections ,? for more information about pi n assignments and external hard ware considerations of these pins. many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or keyboard interrupts as shown in table 2-1 . the peripheral modules have prio rity over the general-purpose i/o functions so that when a peripheral is enabled, th e i/o functions associated with the shared pins are disabled. after reset, the shared peripheral functions are disabled and the pins are configured as inputs (ptxddn = 0). the pin control functions for each pin are confi gured as follows: slew rate control enabled (ptxsen = 1), low drive strength selected (ptxdsn = 0), and internal pull-ups disabled (ptxpen = 0). note not all general-purpose i/o pins are av ailable on all packages. to avoid extra current drain from floating input pins, the user?s reset initialization routine in the application program must either enable on-chip pull-up devices or change the direction of unc onnected pins to outputs so the pins do not float. 6.1 port data and data direction reading and writing of parallel i/ os are performed through the port data registers. the direction, either input or output, is controlled through the port data direction registers. the parallel i/o port function for an individual pin is illustrated in the block diagram shown in figure 6-1 . the data direction control bit (ptxddn) determines whether the out put buffer for the associated pin is enabled, and also controls the source for port data register reads. the in put buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin. when a shared digital function is en abled for a pin, the output buffer is controlled by the shared function. however, the data direction register bi t will continue to contro l the source for reads of the port data register. when a shared analog function is enabled for a pin, both the input and output buffers are disabled. a value of 0 is read for any port data bit wh ere the bit is an input (ptxddn = 0) and the inpu t buffer is disabled. in general, whenever a pin is shared with both an alternate digital func tion and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 80 freescale semiconductor it is a good programming practice to wr ite to the port data register before changing the direction of a port pin to become an output. this ensures that the pin wi ll not be driven momentarily with an old data value that happened to be in the port data register. figure 6-1. parallel i/o block diagram 6.2 pull-up, slew rate, and drive strength associated with the parallel i/o ports is a set of registers locat ed in the high page regi ster space that operate independently of the parallel i/o registers. these registers are used to control pull-ups, slew rate, and drive strength for the pins. an internal pull-up device can be enabled for each port pin by setti ng the corresponding bit in the pull-up enable register (ptxpen). th e pull-up device is disabled if the pin is configured as an output by the parallel i/o control logic or any shared peripheral function regardless of the state of the corresponding pull-up enable register bit. the pull-up de vice is also disabled if the pin is controlled by an analog function. slew rate control can be enabled for each port pin by se tting the corresponding bit in the slew rate control register (ptxsen). when enabled, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pi ns that are configured as inputs. an output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (ptx dsn). when high drive is selected, a pin is capable of sourcing and sinking greater current. even though ev ery i/o pin can be selected as high drive, the user must ensure that the total current source and sink lim its for the mcu are not exceeded. dr ive strength selection is intended to affect the dc behavior of i/o pi ns. however, the ac behavior is also affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this, the emc emi ssions may be affected by enabling pins as high drive. q d q d 1 0 port read ptxddn ptxdn output enable output data input data synchronizer data busclk
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 81 6.3 pin interrupts port a[3:0], port b[3:0] and port c pi ns can be configured as external interrupt inputs and as an external mean of waking the mcu from stop3 or wait low-power modes. the block diagram for each port interrupt logic is shown figure 6-2 . figure 6-2. port interrupt block diagram writing to the ptxpsn bits in the port interrupt pi n select register (ptxps) independently enables or disables each port pin. each port can be configured as edge sensitive or edge and level sensitive based on the ptxmod bit in the port interrupt status and control register (ptxsc). edge sensitivity can be software programmed to be either falling or rising; the level can be either low or high. the polarity of the edge or edge and level sensitivity is select ed using the ptxesn bits in the por t interrupt edge select register (ptxes). synchronous logic is used to detect edges. prior to detecting an edge, enabled port inputs must be at the deasserted logic level. a falling edge is detected when an enabled port input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted le vel) during the next cycle. a rising edge is detected when the input si gnal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 6.3.1 edge only sensitivity a valid edge on an enabled port pin will set ptxif in pt xsc. if ptxie in ptxsc is set, an interrupt request will be presented to the cpu. cl earing of ptxif is accomplished by writing a 1 to ptxack in ptxsc. 6.3.2 edge and level sensitivity a valid edge or level on an enabled por t pin will set ptxif in ptxsc. if pt xie in ptxsc is set, an interrupt request will be presented to the cpu. clearing of ptxif is accomplished by writing a 1 to ptxack in ptxsc provided all enabled port inputs ar e at their deasserted levels. ptxi f will remain se t if any enabled port pin is asserted while attempting to clear by writing a 1 to ptxack. ptxesn dq ck clr v dd ptxmod ptxie port interrupt ff ptxack reset synchronizer ptxif stop bypass stop busclk ptxpsn 0 1 s ptxps0 0 1 s ptxs0 pixn pix n ptx interrupt request
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 82 freescale semiconductor 6.3.3 pull-up/pull-down resistors the port interrupt pins can be confi gured to use an internal pull-up/pull- down resistor usin g the associated i/o port pull enable register. if an in ternal resistor is enabled (ptxpe n=1) and the pin is selected for interrupt (ptxpsn=1), the ptxes regist er is used to select whether the resistor is a pull-up (ptxesn = 0) or a pull-down (ptxesn = 1). 6.3.4 pin interrupt initialization when an interrupt pin is first enable d, it is possible to get a false interrupt flag. to prevent a false interrupt request during pin interr upt initialization, the us er should do the following: 1. mask interrupts by clearing ptxie in ptxsc. 2. select the pin polarity by setting th e appropriate ptxesn bits in ptxes. 3. if using internal pull-up/pull-dow n device, configure the associat ed pull enable bits in ptxpe. 4. enable the interrupt pins by setting the appropriate ptxpsn bits in ptxps. 5. write to ptxack in ptxsc to clear any false interrupts. 6. set ptxie in ptxsc to enable interrupts. 6.4 pin behavior in stop modes pin behavior following execution of a stop instruct ion depends on the stop mode that is entered. an explanation of pin behavior fo r the various stop modes follows: ? stop2 mode is a partial power-down mode, whereby i/o latches are maintained in their state as before the stop instruction was ex ecuted. cpu register status and the state of i/o registers should be saved in ram before the st op instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user shoul d examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initia lized as if a pow er on reset had occurred. if the ppdf bit is 1, i/o data previously stored in ram, before the stop instruction was executed, peripherals may require being initiali zed and restored to their pre-stop condition. the user must then write a 1 to the ppdack bit in th e spmsc2 register. access to i/o is now permitted again in the user application program. ? in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user. 6.5 parallel i/o and pin control registers this section provides information about the registers associated with the parallel i/o ports. the data and data direction registers are located in page zero of the memory map. the pull up, slew rate, drive strength, and interrupt control registers are located in the high page section of the memory map. refer to tables in chapter 4, ?memory ,? for the absolute address assignmen ts for all parallel i/o and their pin control registers. this section refers to registers and control bi ts only by their names. a freescale semiconductor-provided equate or h eader file normally is used to translate these names into the appropriate absolute addresses.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 83 6.5.1 port a registers port a is controlled by the registers listed below. 6.5.1.1 port a data register (ptad) 6.5.1.2 port a data direction register (ptadd) 76543210 r ptad7 ptad6 00 ptad3 ptad2 ptad1 ptad0 w r e s e t :00000000 figure 6-3. port a data register (ptad) table 6-1. ptad register field descriptions field description 7:6 ptad[7:6] port a data register bits ? for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port a pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins be cause reset also configures all port pins as high-impedance inpu ts with pull-ups/pull-downs disabled. 3:0 ptad[3:0] 76543210 r ptadd7 ptadd6 00 ptadd3 ptadd2 ptadd1 ptadd0 w r e s e t :00000000 figure 6-4. port a data direction register (ptadd) table 6-2. ptadd register field descriptions field description 7:6 ptadd[7:6] data direction for port a bits ? these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn. 3:0 ptadd[3:0]
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 84 freescale semiconductor 6.5.1.3 port a pull enable register (ptape) 6.5.1.4 port a slew rate enable register (ptase) 76543210 r ptape7 ptape6 00 ptape3 ptape2 ptape1 ptape0 w r e s e t :00000000 figure 6-5. internal pull enable for port a register (ptape) table 6-3. ptape register field descriptions field description 7:0 ptape[7:6] internal pull enable for port a bits ? each of these control bits determines if the internal pull-up or internal (pin interrupt only) pull-down device is enabled for the associated pta pin. for port a pins that are configured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port a bit n. 1 internal pull-up/pull-down device enabled for port a bit n. 3:0 ptape[3:0] 76543210 r ptase7 ptase6 00 ptase3 ptase2 ptase1 ptase0 w r e s e t :00000000 figure 6-6. slew rate enable for port a register (ptase) table 6-4. ptase register field descriptions field description 7:6 ptase[7:6] output slew rate enable for port a bits ? each of these control bits determines if the output slew rate control is enabled for the associated pta pin. for port a pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port a bit n. 1 output slew rate control enabled for port a bit n. 3:0 ptase[3:0]
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 85 6.5.1.5 port a drive strength selection register (ptads) 6.5.1.6 port a interrupt status and control register (ptasc) 76543210 r ptads7 ptads6 00 ptads3 ptads2 ptads1 ptads0 w r e s e t :00000000 figure 6-7. drive strength selection for port a register (ptads) table 6-5. ptads regist er field descriptions field description 7:6 ptads[7:6] output drive strength selection for port a bits ? each of these control bits selects between low and high output drive for the associated pta pin. for port a pins th at are configured as inputs, these bits have no effect. 0 low output drive strength selected for port a bit n. 1 high output drive strength selected for port a bit n. 3:0 ptads[3:0] 76543210 r0000p t a i f0 ptaie ptamod w ptaack r e s e t :00000000 figure 6-8. port a interrupt status and control register (ptasc) table 6-6. ptasc regist er field descriptions field description 3 ptaif port a interrupt flag ? ptaif indicates when a port a interrupt is detected. wr ites have no effect on ptaif. 0 no port a interrupt detected. 1 port a interrupt detected. 2 ptaack port a interrupt acknowledge ? writing a 1 to ptaack is part of the flag clearing mechanism. ptaack always reads as 0. 1 ptaie port a interrupt enable ? ptaie determines whether a port a interrupt is requested. 0 port a interrupt request not enabled. 1 port a interrupt request enabled. 0 ptamod port a detection mode ? ptamod (along with the ptaes bits) cont rols the detection mo de of the port a interrupt pins. 0 port a pins detect edges only. 1 port a pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 86 freescale semiconductor 6.5.1.7 port a interrupt pin select register (ptaps) 6.5.1.8 port a interrupt edge select register (ptaes) 76543210 r0000 ptaps3 ptaps2 ptaps1 ptaps0 w r e s e t :00000000 figure 6-9. port a interrupt pin select register (ptaps) table 6-7. ptaps register field descriptions field description 3:0 ptaps[3:0] port a interrupt pin selects ? each of the ptapsn bits enable the corresponding port a interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r0000 ptaes3 ptaes2 ptaes1 ptaes0 w r e s e t :00000000 figure 6-10. port a edge select register (ptaes) table 6-8. ptaes register field descriptions field description 3:0 ptaes[3:0] port a edge selects ? each of the ptaesn bits serves a dual purp ose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin interrupt and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin interrupt and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 87 6.5.2 port b registers port b is controlled by the registers listed below. 6.5.2.1 port b data register (ptbd) 6.5.2.2 port b data direction register (ptbdd) 76543210 r ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 w r e s e t :00000000 figure 6-11. port b data register (ptbd) table 6-9. ptbd regist er field descriptions field description 7:0 ptbd[7:0] port b data register bits ? for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port b pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inpu ts with pull-ups/pull-downs disabled. 76543210 r ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 w r e s e t :00000000 figure 6-12. port b data direction register (ptbdd) table 6-10. ptbdd regist er field descriptions field description 7:0 ptbdd[7:0] data direction for port b bits ? these read/write bits control the direction of port b pins and what is read for ptbd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port b bit n and ptbd reads return the contents of ptbdn.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 88 freescale semiconductor 6.5.2.3 port b pull enable register (ptbpe) 6.5.2.4 port b slew rate enable register (ptbse) 76543210 r ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 w r e s e t :00000000 figure 6-13. internal pull enable for port b register (ptbpe) table 6-11. ptbpe register field descriptions field description 7:0 ptbpe[7:0] internal pull enable for port b bits ? each of these control bits determines if the internal pull-up or internal (pin interrupt only) pull-down device is enabled for the a ssociated ptb pin. for port b pins that are configured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port b bit n. 1 internal pull-up/pull-down device enabled for port b bit n. 76543210 r ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 w r e s e t :00000000 figure 6-14. slew rate enable for port b register (ptbse) table 6-12. ptbse register field descriptions field description 7:0 ptbse[7:0] output slew rate enable for port b bits ? each of these control bits determines if the output slew rate control is enabled for the associated ptb pin. for port b pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port b bit n. 1 output slew rate control enabled for port b bit n.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 89 6.5.2.5 port b drive strength selection register (ptbds) 6.5.2.6 port b interrupt status and control regi ster (ptbsc) 76543210 r ptbds7 ptbds6 ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 w reset:00000000 figure 6-15. drive strength selecti on for port b register (ptbds) table 6-13. ptbds register field descriptions field description 7:0 ptbds[7:0] output drive strength selection for port b bits ? each of these control bits selects between low and high output drive for the associated ptb pin. for port b pins th at are configured as inputs, these bits have no effect. 0 low output drive strength selected for port b bit n. 1 high output drive strength selected for port b bit n. 76543210 r0000p t b i f0 ptbie ptbmod w ptback r e s e t :00000000 figure 6-16. port b interrupt status and control register (ptbsc) table 6-14. ptbsc register field descriptions field description 3 ptbif port b interrupt flag ? ptbif indicates when a port b interrupt is detected. writes have no effect on ptbif. 0 no port b interrupt detected. 1 port b interrupt detected. 2 ptback port b interrupt acknowledge ? writing a 1 to ptback is part of the flag clearing mechanism. ptback always reads as 0. 1 ptbie port b interrupt enable ? ptbie determines whether a port b interrupt is requested. 0 port b interrupt request not enabled. 1 port b interrupt request enabled. 0 ptbmod port b detection mode ? ptbmod (along with the ptbes bits) cont rols the detection mo de of the port b interrupt pins. 0 port b pins detect edges only. 1 port b pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 90 freescale semiconductor 6.5.2.7 port b interrupt pin select register (ptbps) 6.5.2.8 port b interrupt edge select register (ptbes) 76543210 r0000 ptbps3 ptbps2 ptbps1 ptbps0 w r e s e t :00000000 figure 6-17. port b interrupt pin select register (ptbps) table 6-15. ptbps register field descriptions field description 3:0 ptbps[3:0] port b interrupt pin selects ? each of the ptbpsn bits enable the corresponding port b interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r0000 ptbes3 ptbes2 ptbes1 ptbes0 w r e s e t :00000000 figure 6-18. port b edge select register (ptbes) table 6-16. ptbes register field descriptions field description 3:0 ptbes[3:0] port b edge selects ? each of the ptbesn bits serves a dual purp ose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin interrupt and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin interrupt and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 91 6.5.3 port c registers port c is controlled by the registers listed below. 6.5.3.1 port c data register (ptcd) 6.5.3.2 port c data direction register (ptcdd) 76543210 r ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 w r e s e t :00000000 figure 6-19. port c data register (ptcd) table 6-17. ptcd register field descriptions field description 7:0 ptcd[7:0] port c data register bits ? for port c pins that are inputs, reads return the logic level on the pin. for port c pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port c pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pull-ups disabled. 76543210 r ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 w reset:00000000 figure 6-20. port c data direction register (ptcdd) table 6-18. ptcdd regist er field descriptions field description 7:0 ptcdd[7:0] data direction for port c bits ? these read/write bits control the direction of port c pins and what is read for ptcd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port c bit n and ptcd reads return the contents of ptcdn.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 92 freescale semiconductor 6.5.3.3 port c pull enable register (ptcpe) 6.5.3.4 port c slew rate enable register (ptcse) 76543210 r ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 w reset:00000000 figure 6-21. internal pull enable for port c register (ptcpe) table 6-19. ptcpe register field descriptions field description 7:0 ptcpe[7:0] internal pull enable for port c bits ? each of these control bits determines if the internal pull-up or internal (pin interrupt only) pull-down device is enabled for the associated ptc pin. for port c pins that are configured as outputs, these bits have no effect a nd the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port c bit n. 1 internal pull-up/pull-down device enabled for port c bit n. 76543210 r ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 w reset:00000000 figure 6-22. slew rate enable for port c register (ptcse) table 6-20. ptcse register field descriptions field description 7:0 ptcse[7:0] output slew rate enable for port c bits ? each of these control bits determines if the output slew rate control is enabled for the associated ptc pin. for port c pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port c bit n. 1 output slew rate control enabled for port c bit n.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 93 6.5.3.5 port c drive strength selection register (ptcds) 6.5.3.6 port c interrupt status and control regi ster (ptcsc) 76543210 r ptcds7 ptcds6 ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 w r e s e t :00000000 figure 6-23. drive strength selecti on for port c register (ptcds) table 6-21. ptcds register field descriptions field description 7:0 ptcds[7:0] output drive strength selection for port c bits ? each of these control bits selects between low and high output drive for the associated ptc pin. for port c pins that are configured as inputs , these bits have no effect. 0 low output drive strength selected for port c bit n. 1 high output drive strength selected for port c bit n. 76543210 r0000p t c i f0 ptcie ptcmod w ptcack reset:00000000 figure 6-24. port c interrupt status and control register (ptcsc) table 6-22. ptcsc register field descriptions field description 3 ptcif port c interrupt flag ? ptcif indicates when a port d interrupt is detected. writes have no effect on ptcif. 0 no port c interrupt detected. 1 port c interrupt detected. 2 ptcack port c interrupt acknowledge ? writing a 1 to ptcack is part of the flag clearing mechanism. ptcack always reads as 0. 1 ptcie port c interrupt enable ? ptcie determines whether a port c interrupt is requested. 0 port c interrupt request not enabled. 1 port c interrupt request enabled. 0 ptcmod port c detection mode ? ptcmod (along with the ptces bits) controls the detection mode of the port c interrupt pins. 0 port c pins detect edges only. 1 port c pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 94 freescale semiconductor 6.5.3.7 port c interrupt pin select register (ptcps) 6.5.3.8 port c interrupt edge select register (ptces) 76543210 r ptcps7 ptcps6 ptcps5 ptcps4 ptcps3 ptcps2 ptcps1 ptcps0 w reset:00000000 figure 6-25. port c interrupt pin select register (ptcps) table 6-23. ptcps register field descriptions field description 7:0 ptcps[7:0] port c interrupt pin selects ? each of the ptcpsn bits enable the corresponding port c interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r ptces7 ptces6 ptces5 ptces4 ptces3 ptces2 ptces1 ptces0 w reset:00000000 figure 6-26. port c edge select register (ptces) table 6-24. ptces register field descriptions field description 7:0 ptces[7:0] port c edge selects ? each of the ptcesn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin interrupt and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin interrupt and detects rising edge/high level for interrupt generation.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 95 chapter 7 central processor unit (s08cpuv3) 7.1 introduction this section provides summary information about the re gisters, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, freescale semiconductor documen t order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code -compatible with the m68hc08 cpu. several instructions and enhanced addressi ng modes were added to improve c compiler efficiency and to support a new background debug system which replaces the m onitor mode of earlier m68hc08 microcontrollers (mcu). 7.1.1 features features of the hcs08 cpu include: ? object code fully upward-compatible with m68hc05 a nd m68hc08 families ? all registers and memory are mappe d to a single 64-kbyte address space ? 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) ? 16-bit index register (h:x) with powerful indexed addressing modes ? 8-bit accumulator (a) ? many instructions treat x as a second general-purpose 8-bit register ? seven addressing modes: ? inherent ? operands in internal registers ? relative ? 8-bit signed offs et to branch destination ? immediate ? operand in next object code byte(s) ? direct ? operand in memory at 0x0000?0x00ff ? extended ? operand anywhere in 64-kbyte address space ? indexed relative to h:x ? five submodes including auto increment ? indexed relative to sp ? impr oves c efficiency dramatically ? memory-to-memory data move instructions with four address mode combinations ? overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ? efficient bit manipulation instructions ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? stop and wait instructions to invoke low-power operating modes
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 96 freescale semiconductor 7.2 programmer?s model and cpu registers figure 7-1 shows the five cpu registers. cpu regi sters are not part of the memory map. figure 7-1. cpu registers 7.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit regist er. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu re sults are often stored into the a accumulator after arithmetic and logical ope rations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data co mes from, or the contents of a can be stored to memory using various addressing m odes to specify the address where data from a will be stored. reset has no effect on the c ontents of the a accumulator. 7.2.2 index register (h:x) this 16-bit register is actually two separate 8-bit regist ers (h and x), which often work together as a 16-bit address pointer where h holds the upp er byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc 05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8- bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, co mplemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or tr ansferred to a where arithm etic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is fo rced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 97 7.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available locati on on the automatic last-in-first-out (lifo) stack. the stack may be lo cated anywhere in the 64-kbyte a ddress space that has ram and can be any size up to the amount of available ram. the stac k is used to automaticall y save the return address for subroutine calls, the return address and cpu regi sters during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate valu e to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc 05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ra m (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was includ ed for compatibility with the m68hc05 family and is seldom used in new hcs08 progr ams because it only affects the low- order half of the stack pointer. 7.2.4 program counter (pc) the program counter is a 16-bit register that contai ns the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an in struction or operand is fetched. ju mp, branch, interrupt, and return operations load the program counter with an address ot her than that of the next sequential location. this is called a change-of-flow. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the first in struction that will be execu ted after exiting the reset state. 7.2.5 condition code register (ccr) the 8-bit condition code register contai ns the interrupt mask (i) and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set pe rmanently to 1. the following paragraphs describe the functions of the condition code bits in general term s. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1.
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 98 freescale semiconductor figure 7-2. condition code register table 7-1. ccr register field descriptions field description 7 v two?s complement overflow flag ? the cpu sets the overflow flag when a two?s complement overflow occurs. the signed branch instructions bgt, bg e, ble, and blt use the overflow flag. 0 no overflow 1overflow 4 h half-carry flag ? the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operati on. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction us es the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ? when the interrupt mask is set, all maska ble cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers ar e saved on the stack, but before the firs t instruction of the interrupt service routine is executed. interrupts are not recognized at the inst ruction boundary after any instruction that clears i (cli or tap). this ensures that the next instru ction after a cli or tap will always be execut ed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ? the cpu sets the negative flag when an arithmetic operation, logi c operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most significant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ? the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1zero result 0 c carry/borrow flag ? the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation require s a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 0 no carry out of bit 7 1 carry out of bit 7 condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow 70 ccr c v11hinz
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 99 7.3 addressing modes addressing modes define the way th e cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/out put (i/o) ports share a single 64-kbyt e linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access va riables in ram can also be used to acce ss i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, m ove instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and db nz use one addressing mode to specify the location of an operand for a test and then use relative addres sing mode to specify the branch destination address when the tested condition is true . for brclr, brset, cbeq, and dbnz , the addressing mode listed in the instruction set tables is the addressing mode need ed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination locatio n for branch instructions. a signed 8-bit offset value is located in the memory location immediate ly following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 immediate addressing mode (imm) in immediate addressing mode, the op erand needed to complete the inst ruction is included in the object code immediately followi ng the instruction opcode in memory. in the case of a 16-bi t immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memo ry location after that. 7.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000?0x00ff). during execution a 16-bit address is formed by concatenati ng an implied 0x00 for the high-order half of the address and th e direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory efficien t than specifying a complete 16-bit address for the operand.
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 100 freescale semiconductor 7.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 indexed addressing mode indexed addressing mode has seven variations including five that use the 16-bit h:x index register pair and two that use the stack po inter as the base reference. 7.3.6.1 indexed, no offset (ix) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. 7.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit va lue in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 101 7.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 special operations the cpu performs a few special opera tions that are similar to instruct ions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop a nd wait directly affect other mcu circuitry. this section provides additional informat ion about these operations. 7.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determin es the source, refer to the resets, interrupts, and system configuration chapter. the reset event is considered conc luded when the sequence to determin e whether the reset came from an internal source is done and when the reset pin is no longer asse rted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0x fffe and 0xffff and to fill the instruction queue in preparation for execution of the first program instruction. 7.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority in terrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program info rmation starting at the address i ndicated by the interrupt vector to fill the instruction queue in preparation for ex ecution of the first instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routin e. although it is possible to clear th e i bit with an instruction in the
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 102 freescale semiconductor interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are di fficult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the hi gh-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt se quence. the user must use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certa in that the interr upt service routine does not use any instructions or auto-increment addressing modes that might change the value of h. the software interrupt (swi) instruction is like a ha rdware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumpt ion while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event oc curs, the cpu clocks will resume and the interrupt or reset even t will be processed normally. if a serial background comma nd is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu cloc ks will resume and th e cpu will enter activ e background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu ev en if it is in wait mode. 7.4.4 stop mode operation usually, all system clocks, includi ng the crystal oscillator (when used ), are halted during stop mode to minimize power consumption. in such systems, external circui try is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be configured to keep a minimum set of clocks running in stop mode. this optionally allows an internal periodi c signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial back ground command is issued to the mc u through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial backgr ound commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode de pends on the particular hcs08 and whether the osc illator was stopped in stop mode. refer to the modes of operation chapter for more details.
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 103 7.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compar ed to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to st op processing user instructions and enter the active background mode. the only way to re sume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program re aches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program. 7.5 hcs08 instruction set summary table 7-2 provides a summary of the hcs08 instruction se t in all possible addressing modes. the table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode vari ation of each instruction. table 7-2. instruction set summary (sheet 1 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c adc # opr8i adc opr8a adc opr16a adc oprx16,x adc oprx8 ,x adc ,x adc oprx16,sp adc oprx8 ,sp add with carry a (a) + (m) + (c) imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9e d9 9e e9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 ? add # opr8i add opr8a add opr16a add oprx16,x add oprx8 ,x add ,x add oprx16,sp add oprx8 ,sp add without carry a (a) + (m) imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9e db 9e eb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 ? ais # op r8i add immediate value (signed) to stack pointer sp (sp) + (m) imm a7 ii 2 pp ?11? ???? aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) imm af ii 2 pp ?11? ???? and # opr8i and opr8a and opr16a and oprx16,x and oprx8 ,x and ,x and oprx16,sp and oprx8 ,sp logical and a (a) & (m) imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9e d4 9e e4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011? ? ?
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 104 freescale semiconductor asl opr8a asla aslx asl oprx8 ,x asl ,x asl oprx8 ,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ?? asr opr8a asra asrx asr oprx8 ,x asr ,x asr oprx8 ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e 67 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11? ? bcc rel branch if carry bit clear (if c = 0) rel 24 rr 3 ppp ?11? ???? bclr n,opr8a clear bit n in memory (mn 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ?11? ? ??? bcs rel branch if carry bit set (if c = 1) (same as blo) rel 25 rr 3 ppp ?11? ???? beq rel branch if equal (if z = 1) rel 27 rr 3 ppp ?11? ???? bge rel branch if greater than or equal to (if n v = 0) (signed) rel 90 rr 3 ppp ?11? ???? bgnd enter active background if enbdm=1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ fp...ppp ?11? ???? bgt rel branch if greater than (if z | (n v) = 0) (signed) rel 92 rr 3 ppp ?11? ???? bhcc rel branch if half carry bit clear (if h = 0) rel 28 rr 3 ppp ?11? ???? bhcs rel branch if half carry bit set (if h = 1) rel 29 rr 3 ppp ?11? ???? bhi rel branch if higher (if c | z = 0) rel 22 rr 3 ppp ?11? ???? bhs rel branch if higher or same (if c = 0) (same as bcc) rel 24 rr 3 ppp ?11? ???? bih rel branch if irq pin high (if irq pin = 1) rel 2f rr 3 ppp ?11? ???? bil rel branch if irq pin low (if irq pin = 0) rel 2e rr 3 ppp ?11? ???? bit # opr8i bit opr8a bit opr16a bit oprx16,x bit oprx8 ,x bit ,x bit oprx16,sp bit oprx8 ,sp bit test (a) & (m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9e d5 9e e5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011? ? ? table 7-2. instruction set summary (sheet 2 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c c b0 b7 0 b0 b7 c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 105 ble rel branch if less than or equal to (if z | (n v) = 1) (signed) rel 93 rr 3 ppp ?11? ???? blo rel branch if lower (if c = 1) (same as bcs) rel 25 rr 3 ppp ?11? ???? bls rel branch if lower or same (if c | z = 1) rel 23 rr 3 ppp ?11? ???? blt rel branch if less than (if n v = 1) (signed) rel 91 rr 3 ppp ?11? ???? bmc rel branch if interrupt mask clear (if i = 0) rel 2c rr 3 ppp ?11? ???? bmi rel branch if minus (if n = 1) rel 2b rr 3 ppp ?11? ???? bms rel branch if interrupt mask set (if i = 1) rel 2d rr 3 ppp ?11? ???? bne rel branch if not equal (if z = 0) rel 26 rr 3 ppp ?11? ???? bpl rel branch if plus (if n = 0) rel 2a rr 3 ppp ?11? ???? bra rel branch always (if i = 1) rel 20 rr 3 ppp ?11? ???? brclr n,opr8a,rel branch if bit n in memory clear (if (mn) = 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ?11? ??? brn rel branch never (if i = 0) rel 21 rr 3 ppp ?11? ???? brset n, opr8a ,rel branch if bit n in memory set (if (mn) = 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ?11? ??? bset n,opr8a set bit n in memory (mn 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ?11? ? ??? bsr rel branch to subroutine pc (pc) + $0002 push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 pc (pc) + rel rel ad rr 5 ssppp ?11? ???? cbeq opr8a,rel cbeqa # opr8i ,rel cbeqx # opr8i ,rel cbeq oprx8 ,x+, rel cbeq ,x+, rel cbeq oprx8 ,sp, rel compare and... branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e 61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 rpppp pppp pppp rpppp rfppp prpppp ?11? ???? table 7-2. instruction set summary (sheet 3 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 106 freescale semiconductor clc clear carry bit (c 0) inh 98 1 p ?11? ???0 cli clear interrupt mask bit (i 0) inh 9a 1 p ?11? 0??? clr opr8a clra clrx clrh clr oprx8 ,x clr ,x clr oprx8 ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e 6f dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 011? ?01? cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8 ,sp compare accumulator with memory a ? m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9e d1 9e e1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 ?? com opr8a coma comx com oprx8 ,x com ,x com oprx8 ,sp complement m (m )= $ff ? (m) (one?s complement) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) dir inh inh ix1 ix sp1 33 43 53 63 73 9e 63 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 011? ? 1 cphx opr16a cphx #opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ? (m:m + $0001) (ccr updated but operands not changed) ext imm dir sp1 3e 65 75 9e f3 hh ll jj kk dd ff 6 3 5 6 prrfpp ppp rrfpp prrfpp 11 ?? cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8 ,x cpx ,x cpx oprx16 ,sp cpx oprx8 ,sp compare x (index register low) with memory x ? m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9e d3 9e e3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 ?? daa decimal adjust accumulator after add or adc of bcd values inh 72 1 p u11? ? dbnz opr8a,rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp, rel decrement a, x, or m and branch if not zero (if (result) 0) dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e 6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 rfwpppp fppp fppp rfwpppp rfwppp prfwpppp ?11? ???? dec opr8a deca decx dec oprx8 ,x dec ,x dec oprx8 ,sp decrement m (m) ? $01 a (a) ? $01 x (x) ? $01 m (m) ? $ 01 m (m) ? $01 m (m) ? $01 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e 6a dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ?? ? table 7-2. instruction set summary (sheet 4 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 107 div divide a (h:a) (x); h remainder inh 52 6 fffffp ?11? ?? eor # opr8i eor opr8a eor opr16a eor oprx16 ,x eor oprx8 ,x eor ,x eor oprx16 ,sp eor oprx8 ,sp exclusive or memory with accumulator a (a m) imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9e d8 9e e8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011? ? ? inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + $01 a (a) + $01 x (x) + $01 m (m) + $01 m (m) + $01 m (m) + $01 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e 6c dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwp p 11? ? ? jmp opr8a jmp opr16a jmp oprx16,x jmp oprx8 ,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 ppp pppp pppp ppp ppp ?11? ???? jsr opr8a jsr opr16a jsr oprx16 ,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 ssppp psspp p psspp p ssppp ssppp ?11? ???? lda # opr8i lda opr8a lda opr16a lda oprx16,x lda oprx8 ,x lda ,x lda oprx16,sp lda oprx8 ,sp load accumulator from memory a (m) imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9e d6 9e e6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011? ? ? ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16,x ldhx oprx8 ,x ldhx oprx8 ,sp load index register (h:x) h:x ( m:m + $0001 ) imm dir ext ix ix2 ix1 sp1 45 55 32 9e ae 9e be 9e ce 9e fe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 ppp rrpp prrpp prrfp pprrp p prrpp prrpp 011? ? ? ldx # opr8i ldx opr8a ldx opr16a ldx oprx16,x ldx oprx8 ,x ldx ,x ldx oprx16,sp ldx oprx8 ,sp load x (index register low) from memory x (m) imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9e de 9e ee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011? ? ? table 7-2. instruction set summary (sheet 5 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 108 freescale semiconductor lsl opr8a lsla lslx lsl oprx8 ,x lsl ,x lsl oprx8 ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ?? lsr opr8a lsra lsr x lsr oprx8 ,x lsr ,x lsr oprx8 ,sp logical shift right dir inh inh ix1 ix sp1 34 44 54 64 74 9e 64 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ??0 mov opr8a ,opr8a mov opr8a,x+ mov # opr8i , opr8a mov ,x+, opr8a move (m) destination (m) source in ix+/dir and dir/ix+ modes, h:x (h:x) + $0001 dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 rpwpp rfwpp pwpp rfwpp 011? ? ? mul unsigned multiply x:a (x) (a) inh 42 5 ffffp ?110 ???0 neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate m ? (m) = $00 ? (m) (two?s complement) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e 60 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ?? nop no operation ? uses 1 bus cycle inh 9d 1 p ?11? ? ??? nsa nibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 p ?11? ???? ora # opr8i ora opr8a ora opr16a ora oprx16 ,x ora oprx8 ,x ora ,x ora oprx16 ,sp ora oprx8 ,sp inclusive or accumulator and memory a (a) | (m) imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9e da 9e ea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011? ? ? psha push accumulator onto stack push (a); sp (sp) ? $0001 inh 87 2 sp ?11? ???? pshh push h (index register high) onto stack push (h); sp (sp) ? $0001 inh 8b 2 sp ?11? ???? pshx push x (index register low) onto stack push (x); sp (sp) ? $0001 inh 89 2 sp ?11? ???? pula pull accumulator from stack sp (sp + $0001); pull ( a ) inh 86 3 ufp ?11? ???? pulh pull h (index register high) from stack sp (sp + $0001); pull ( h) inh 8a 3 ufp ?11? ???? pulx pull x (index register low) from stack sp (sp + $0001); pull ( x ) inh 88 3 ufp ?11? ???? table 7-2. instruction set summary (sheet 6 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c c b0 b7 0 b0 b7 c 0
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 109 rol opr8a rola rolx rol oprx8 ,x rol ,x rol oprx8 ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e 69 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ?? ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e 66 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ?? rsp reset stack pointer (low byte) spl $ff (high byte not affected) inh 9c 1 p ?11? ???? rti return from interrupt sp (sp ) + $0001; pull (ccr) sp (sp ) + $0001; pull (a) sp (sp) + $0001; pull (x) sp (sp) + $0001; pull (pch) sp (sp) + $0001; pull (pcl) inh 80 9 uuuuufppp 11 rts return from subroutine sp sp + $0001 ; pull ( pch) sp sp + $0001; pull (pcl) inh 81 5 ufppp ?11? ???? sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8 ,x sbc ,x sbc oprx16 ,sp sbc oprx8 ,sp subtract with carry a (a) ? (m) ? (c) imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9e d2 9e e2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 ?? sec set carry bi t (c 1) inh 99 1 p ?11? ???1 sei set interrupt mask bit (i 1) inh 9b 1 p ?11? 1??? sta opr8a sta opr16a sta oprx16,x sta oprx8 ,x sta ,x sta oprx16,sp sta oprx8 ,sp store accumulator in memory m (a) dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9e d7 9e e7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 011? ? ? sthx opr8a sthx opr16a sthx oprx8 ,sp store h:x (index reg.) (m:m + $0001) (h:x) dir ext sp1 35 96 9e ff dd hh ll ff 4 5 5 wwpp pwwpp pwwpp 011? ? ? stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing inh 8e 2 fp... ?11? 0??? table 7-2. instruction set summary (sheet 7 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c c b0 b7 b0 b7 c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 110 freescale semiconductor stx opr8a stx opr16a stx oprx16,x stx oprx8 ,x stx ,x stx oprx16,sp stx oprx8 ,sp store x (low 8 bits of index register) in memory m (x) dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9e df 9e ef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 011? ? ? sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8 ,x sub ,x sub oprx16 ,sp sub oprx8 ,sp subtract a (a) ? (m) imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9e d0 9e e0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 ?? sw i softwar e interrupt pc (pc) + $0001 push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 push (x); sp (sp) ? $0001 push (a); sp (sp) ? $0001 push (ccr); sp (sp) ? $0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte inh 83 11 sssssvvfppp ?11? 1??? tap transfer accumulator to ccr ccr (a) inh 84 1 p 11 tax transfer accumulator to x (index register low) x (a) inh 97 1 p ?11? ???? tpa transfer ccr to accumulator a (ccr) inh 85 1 p ?11? ???? tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ? $00 (a) ? $00 (x) ? $00 (m) ? $00 (m) ? $00 (m) ? $00 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e 6d dd ff ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 011? ? ? tsx transfer sp to index reg. h:x (sp) + $0001 inh 95 2 fp ?11? ???? txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 p ?11? ???? table 7-2. instruction set summary (sheet 8 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 111 txs transfer index reg. to sp sp (h:x) ? $0001 inh 94 2 fp ?11? ???? wait enable interrupts; wait for interrupt i bit 0; halt cpu inh 8f 2+ fp... ?11? 0??? source form: everything in the source forms columns, except expressions in italic characters , is literal information which must appear in the assembly source file exactly as shown. the initial 3- to 5-letter mnemonic and t he characters (#, ( ) and +) are always a liter al characters. n any label or expression that evaluates to a single integer in the range 0-7. opr8i any label or expression that eval uates to an 8-bit immediate value. opr16i any label or expression that eval uates to a 16-bit immediate value. opr8a any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a any label or expression that evaluates to a 16-bit address. oprx8 any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel any label or expression that refers to an address that is within ?128 to +127 locations from the start of the next instruction. operation symbols: a accumulator ccr condition code register h index register high byte m memory location n any bit opr operand (one or two bytes) pc program counter pch program counter high byte pcl program counter low byte rel relative program counter offset byte sp stack pointer spl stack pointer low byte x index register low byte & logical and | logical or logical exclusive or ( ) contents of + add ? subtract, negation (two?s complement) multiply divide # immediate value loaded with : concatenated with addressing modes: dir direct addressing mode ext extended addressing mode imm immediate addressing mode inh inherent addressing mode ix indexed, no offset addressing mode ix1 indexed, 8-bit offset addressing mode ix2 indexed, 16-bit offset addressing mode ix+ indexed, no offset, pos t increment addressing mode ix1+ indexed, 8-bit offset, post increment addressing mode rel relative addressing mode sp1 stack pointer, 8-bit offset addressing mode sp2 stack pointer 16-bit offset addressing mode cycle-by-cycle codes: f free cycle. this indicates a cycle where the cpu does not require use of the system buses. an f cycle is always one cycle of the system bus clock and is always a read cycle. p program fetch; read from next consecutive location in program memory r read 8-bit operand s push (write) one byte onto stack u pop (read) one byte from stack v read vector from $ffxx (high byte first) w write 8-bit operand ccr bits: voverflow bit h half-carry bit i interrupt mask n negative bit z zero bit c carry/borrow bit ccr effects: set or cleared ? not affected u undefined table 7-2. instruction set summary (sheet 9 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 112 freescale semiconductor table 7-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modi fy-write control register/memory 00 5 brset0 3dir 10 5 bset0 2dir 20 3 bra 2rel 30 5 neg 2dir 40 1 nega 1inh 50 1 negx 1inh 60 5 neg 2ix1 70 4 neg 1ix 80 9 rti 1inh 90 3 bge 2rel a0 2 sub 2imm b0 3 sub 2dir c0 4 sub 3 ext d0 4 sub 3ix2 e0 3 sub 2ix1 f0 3 sub 1ix 01 5 brclr0 3dir 11 5 bclr0 2dir 21 3 brn 2rel 31 5 cbeq 3dir 41 4 cbeqa 3imm 51 4 cbeqx 3imm 61 5 cbeq 3ix1+ 71 5 cbeq 2ix+ 81 6 rts 1inh 91 3 blt 2rel a1 2 cmp 2imm b1 3 cmp 2dir c1 4 cmp 3 ext d1 4 cmp 3ix2 e1 3 cmp 2ix1 f1 3 cmp 1ix 02 5 brset1 3dir 12 5 bset1 2dir 22 3 bhi 2rel 32 5 ldhx 3ext 42 5 mul 1inh 52 6 div 1inh 62 1 nsa 1inh 72 1 daa 1inh 82 5+ bgnd 1inh 92 3 bgt 2rel a2 2 sbc 2imm b2 3 sbc 2dir c2 4 sbc 3 ext d2 4 sbc 3ix2 e2 3 sbc 2ix1 f2 3 sbc 1ix 03 5 brclr1 3dir 13 5 bclr1 2dir 23 3 bls 2rel 33 5 com 2dir 43 1 coma 1inh 53 1 comx 1inh 63 5 com 2ix1 73 4 com 1ix 83 11 swi 1inh 93 3 ble 2rel a3 2 cpx 2imm b3 3 cpx 2dir c3 4 cpx 3 ext d3 4 cpx 3ix2 e3 3 cpx 2ix1 f3 3 cpx 1ix 04 5 brset2 3dir 14 5 bset2 2dir 24 3 bcc 2rel 34 5 lsr 2dir 44 1 lsra 1inh 54 1 lsrx 1inh 64 5 lsr 2ix1 74 4 lsr 1ix 84 1 ta p 1inh 94 2 txs 1inh a4 2 and 2imm b4 3 and 2dir c4 4 and 3 ext d4 4 and 3ix2 e4 3 and 2ix1 f4 3 and 1ix 05 5 brclr2 3dir 15 5 bclr2 2dir 25 3 bcs 2rel 35 4 sthx 2dir 45 3 ldhx 3imm 55 4 ldhx 2dir 65 3 cphx 3imm 75 5 cphx 2dir 85 1 tpa 1inh 95 2 tsx 1inh a5 2 bit 2imm b5 3 bit 2dir c5 4 bit 3 ext d5 4 bit 3ix2 e5 3 bit 2ix1 f5 3 bit 1ix 06 5 brset3 3dir 16 5 bset3 2dir 26 3 bne 2rel 36 5 ror 2dir 46 1 rora 1inh 56 1 rorx 1inh 66 5 ror 2ix1 76 4 ror 1ix 86 3 pula 1inh 96 5 sthx 3ext a6 2 lda 2imm b6 3 lda 2dir c6 4 lda 3 ext d6 4 lda 3ix2 e6 3 lda 2ix1 f6 3 lda 1ix 07 5 brclr3 3dir 17 5 bclr3 2dir 27 3 beq 2rel 37 5 asr 2dir 47 1 asra 1inh 57 1 asrx 1inh 67 5 asr 2ix1 77 4 asr 1ix 87 2 psha 1inh 97 1 ta x 1inh a7 2 ais 2imm b7 3 sta 2dir c7 4 sta 3 ext d7 4 sta 3ix2 e7 3 sta 2ix1 f7 2 sta 1ix 08 5 brset4 3dir 18 5 bset4 2dir 28 3 bhcc 2rel 38 5 lsl 2dir 48 1 lsla 1inh 58 1 lslx 1inh 68 5 lsl 2ix1 78 4 lsl 1ix 88 3 pulx 1inh 98 1 clc 1inh a8 2 eor 2imm b8 3 eor 2dir c8 4 eor 3 ext d8 4 eor 3ix2 e8 3 eor 2ix1 f8 3 eor 1ix 09 5 brclr4 3dir 19 5 bclr4 2dir 29 3 bhcs 2rel 39 5 rol 2dir 49 1 rola 1inh 59 1 rolx 1inh 69 5 rol 2ix1 79 4 rol 1ix 89 2 pshx 1inh 99 1 sec 1inh a9 2 adc 2imm b9 3 adc 2dir c9 4 adc 3 ext d9 4 adc 3ix2 e9 3 adc 2ix1 f9 3 adc 1ix 0a 5 brset5 3dir 1a 5 bset5 2dir 2a 3 bpl 2rel 3a 5 dec 2dir 4a 1 deca 1inh 5a 1 decx 1inh 6a 5 dec 2ix1 7a 4 dec 1ix 8a 3 pulh 1inh 9a 1 cli 1inh aa 2 ora 2imm ba 3 ora 2dir ca 4 ora 3 ext da 4 ora 3ix2 ea 3 ora 2ix1 fa 3 ora 1ix 0b 5 brclr5 3dir 1b 5 bclr5 2dir 2b 3 bmi 2rel 3b 7 dbnz 3dir 4b 4 dbnza 2inh 5b 4 dbnzx 2inh 6b 7 dbnz 3ix1 7b 6 dbnz 2ix 8b 2 pshh 1inh 9b 1 sei 1inh ab 2 add 2imm bb 3 add 2dir cb 4 add 3 ext db 4 add 3ix2 eb 3 add 2ix1 fb 3 add 1ix 0c 5 brset6 3dir 1c 5 bset6 2dir 2c 3 bmc 2rel 3c 5 inc 2dir 4c 1 inca 1inh 5c 1 incx 1inh 6c 5 inc 2ix1 7c 4 inc 1ix 8c 1 clrh 1inh 9c 1 rsp 1inh bc 3 jmp 2dir cc 4 jmp 3 ext dc 4 jmp 3ix2 ec 3 jmp 2ix1 fc 3 jmp 1ix 0d 5 brclr6 3dir 1d 5 bclr6 2dir 2d 3 bms 2rel 3d 4 tst 2dir 4d 1 tsta 1inh 5d 1 tstx 1inh 6d 4 tst 2ix1 7d 3 tst 1ix 9d 1 nop 1inh ad 5 bsr 2rel bd 5 jsr 2dir cd 6 jsr 3 ext dd 6 jsr 3ix2 ed 5 jsr 2ix1 fd 5 jsr 1ix 0e 5 brset7 3dir 1e 5 bset7 2dir 2e 3 bil 2rel 3e 6 cphx 3ext 4e 5 mov 3dd 5e 5 mov 2dix+ 6e 4 mov 3imd 7e 5 mov 2ix+d 8e 2+ stop 1inh 9e page 2 ae 2 ldx 2imm be 3 ldx 2dir ce 4 ldx 3 ext de 4 ldx 3ix2 ee 3 ldx 2ix1 fe 3 ldx 1ix 0f 5 brclr7 3dir 1f 5 bclr7 2dir 2f 3 bih 2rel 3f 5 clr 2dir 4f 1 clra 1inh 5f 1 clrx 1inh 6f 5 clr 2ix1 7f 4 clr 1ix 8f 2+ wait 1inh 9f 1 txa 1inh af 2 aix 2imm bf 3 stx 2dir cf 4 stx 3 ext df 4 stx 3ix2 ef 3 stx 2ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 113 bit-manipulation branch read-modi fy-write control register/memory 9e60 6 neg 3sp1 9ed0 5 sub 4sp2 9ee0 4 sub 3sp1 9e61 6 cbeq 4sp1 9ed1 5 cmp 4sp2 9ee1 4 cmp 3sp1 9ed2 5 sbc 4sp2 9ee2 4 sbc 3sp1 9e63 6 com 3sp1 9ed3 5 cpx 4sp2 9ee3 4 cpx 3sp1 9ef3 6 cphx 3sp1 9e64 6 lsr 3sp1 9ed4 5 and 4sp2 9ee4 4 and 3sp1 9ed5 5 bit 4sp2 9ee5 4 bit 3sp1 9e66 6 ror 3sp1 9ed6 5 lda 4sp2 9ee6 4 lda 3sp1 9e67 6 asr 3sp1 9ed7 5 sta 4sp2 9ee7 4 sta 3sp1 9e68 6 lsl 3sp1 9ed8 5 eor 4sp2 9ee8 4 eor 3sp1 9e69 6 rol 3sp1 9ed9 5 adc 4sp2 9ee9 4 adc 3sp1 9e6a 6 dec 3sp1 9eda 5 ora 4sp2 9eea 4 ora 3sp1 9e6b 8 dbnz 4sp1 9edb 5 add 4sp2 9eeb 4 add 3sp1 9e6c 6 inc 3sp1 9e6d 5 tst 3sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4ix2 9ece 5 ldhx 3ix1 9ede 5 ldx 4sp2 9eee 4 ldx 3sp1 9efe 5 ldhx 3sp1 9e6f 6 clr 3sp1 9edf 5 stx 4sp2 9eef 4 stx 3sp1 9eff 5 sthx 3sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3sp1 hcs08 cycles instruction mnemonic addressing mode table 7-3. opcode map (sheet 2 of 2)
chapter 7 central processor unit (s08cpuv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 114 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 115 chapter 8 internal clock source (s08icsv2) 8.1 introduction the internal clock source (ics) m odule provides clock source choices for the mcu. the module contains a frequency-locked loop (fll) as a cl ock source that is controllable by either an internal or an external reference clock. the module can provide this fll clock or either of the internal or external reference clocks as a source for the mcu sy stem clock. there are also signals provided to control a low power oscillator (xosc) module to allow th e use of an external cr ystal/resonator as the external reference clock. whichever clock source is chosen, it is passed through a reduced bus divi der (bdiv) which allows a lower final output clock frequency to be derived. the bus frequency is half of the ic sout frequency. after reset, the ics is configured for fei mode and bdiv resets to 01 to introduce an extra divide-by- two before icsout. therefore, the bus frequency is f dco /4. at por, the trim and ftrim are reset to 0x80 and 0, respectively. theref ore, the dco frequency is f dco_ut . for other resets, the trim settings keep the value that was present before the reset. note refer to section 1.3, ?system clock distribution? , for a detailed view of the distribution of clock sources throughout the mcu. 8.1.1 module configuration when the internal reference is enabled in stop mode (irefsten = 1), the voltage regulator must also be enabled in stop mode by setting the lvde and lvdse bits in the spmsc1 register. figure 8-1 shows the mc9s08el32 block diagram with the ics highlighted.
chapter 8 internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 116 freescale semiconductor figure 8-1. block diagram high lighting ics block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 117 8.1.2 features key features of the ics module follow . for device specific in formation, refer to the ics characteristics in the electricals section of the documentation. ? frequency-locked loop (fll) is trimmable for accuracy ? 0.2% resolution using in ternal 32khz reference ? 2% deviation over voltage and temper ature using internal 32khz reference ? internal or external reference clocks up to 5mhz can be used to control the fll ? 3 bit select for reference divider is provided ? internal reference clock has 9 trim bits available ? internal or external reference clocks can be selected as the clock source for the mcu ? whichever clock is selected as the source can be divided down ? 2 bit select for clock divider is provided ? allowable dividers are: 1, 2, 4, 8 ? bdc clock is provided as a cons tant divide by 2 of the dco output ? control signals for a low power oscillator as the external reference clock are provided ? hgo, range, erefs, erclken, erefsten ? fll engaged internal mode is auto matically selected out of reset 8.1.3 block diagram figure 8-2 is the ics block diagram.
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 118 freescale semiconductor figure 8-2. internal clock source (ics) block diagram 8.1.4 modes of operation there are seven modes of operation for the ics: fei, fee, fbi, fbilp, fbe, fbelp, and stop. 8.1.4.1 fll engaged interna l (fei) in fll engaged internal mode, which is the default mode, the ics supplies a clock derived from the fll which is controlled by the internal reference clock. the bdc clock is supplied from the fll. 8.1.4.2 fll engaged external (fee) in fll engaged external mode, the ics supplies a cloc k derived from the fll wh ich is controlled by an external reference clock. the bd c clock is supplied from the fll. 8.1.4.3 fll bypassed interna l (fbi) in fll bypassed internal mode, the fll is enabled and controlled by the internal reference clock, but is bypassed. the ics supplies a clock derived from the in ternal reference clock. th e bdc clock is supplied from the fll. dco filter rdiv trim / 2 9 external reference irefs clock source block clks n=0-7 / 2 n n=0-3 / 2 n internal reference clock bdiv 9 icslclk icsout icsirclk erefs range erefsten hgo optional irefsten icserclk internal clock source block lp icsffclk erclken irclken dcoout fll rdiv_clk
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 119 8.1.4.4 fll bypassed interna l low power (fbilp) in fll bypassed internal low power mode, the fll is disabled and bypassed, a nd the ics supplies a clock derived from the internal reference clock. the bdc clock is not available. 8.1.4.5 fll bypassed externa l (fbe) in fll bypassed external mode, the fll is enabled a nd controlled by an external reference clock, but is bypassed. the ics supplies a clock derive d from the external reference clock. the external reference clock can be an external crystal/ resonator supplied by an osc controlled by th e ics, or it can be another external clock source. the bdc clock is supplied from the fll. 8.1.4.6 fll bypassed externa l low power (fbelp) in fll bypassed external low power mode, the fll is disabled and bypassed, and the ics supplies a clock derived from the external reference clock. the external reference clock can be an external crystal/resonator supplied by an osc controlled by the ics, or it can be another extern al clock source. the bdc clock is not available. 8.1.4.7 stop (stop) in stop mode the fll is disabled and the internal or external reference clocks can be selected to be enabled or disabled. the bdc clock is not available and the ics does not provide an mcu clock source. 8.2 external signal description there are no ics signals that connect off chip. 8.3 register definition figure 8-1 is a summary of ics registers. table 8-1. ics register summary name 76543 2 1 0 icsc1 r clks rdiv irefs irclken irefsten w icsc2 r bdiv range hgo lp erefs erclken erefsten w icstrm r trim w icssc r 0 0 0 irefst clkst oscinit ftrim w
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 120 freescale semiconductor 8.3.1 ics control register 1 (icsc1) 7 6543210 r clks rdiv irefs irclken irefsten w reset: 0 0 0 0 0 1 0 0 figure 8-3. ics control register 1 (icsc1) table 8-2. ics control register 1 field descriptions field description 7:6 clks clock source select ? selects the clock source that controls the bus frequency. the actual bus frequency depends on the value of the bdiv bits. 00 output of fll is selected. 01 internal reference clock is selected. 10 external reference clock is selected. 11 reserved, defaults to 00. 5:3 rdiv reference divider ? selects the amount to divide down the fll reference clock selected by the irefs bits. resulting frequency must be in the range 31.25 khz to 39.0625 khz. 000 encoding 0 ? divides reference clock by 1 (reset default) 001 encoding 1 ? divides reference clock by 2 010 encoding 2 ? divides reference clock by 4 011 encoding 3 ? divides reference clock by 8 100 encoding 4 ? divides reference clock by 16 101 encoding 5 ? divides reference clock by 32 110 encoding 6 ? divides reference clock by 64 111 encoding 7 ? divides reference clock by 128 2 irefs internal reference select ? the irefs bit selects the refe rence clock source for the fll. 1 internal reference clock selected 0 external reference clock selected 1 irclken internal reference clock enable ? the irclken bit enables the internal reference clock for use as icsirclk. 1 icsirclk active 0 icsirclk inactive 0 irefsten internal refere nce stop enable ? the irefsten bit controls whether or not the internal reference clock remains enabled when the ics enters stop mode. 1 internal reference clock stays enabled in stop if irclken is set or if ics is in fei, fbi, or fbilp mode before entering stop 0 internal reference clock is disabled in stop
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 121 8.3.2 ics control register 2 (icsc2) 7 6543210 r bdiv range hgo lp erefs erclken erefsten w r e s e t :0 1000000 figure 8-4. ics control register 2 (icsc2) table 8-3. ics control register 2 field descriptions field description 7:6 bdiv bus frequency divider ? selects the amount to divide down the clock source selected by the clks bits. this controls the bus frequency. 00 encoding 0 ? divides selected clock by 1 01 encoding 1 ? divides selected clock by 2 (reset default) 10 encoding 2 ? divides selected clock by 4 11 encoding 3 ? divides selected clock by 8 5 range frequency range select ? selects the frequency range for the external oscillator. 1 high frequency range selected for the external oscillator 0 low frequency range selected for the external oscillator 4 hgo high gain oscillator select ? the hgo bit controls the exte rnal oscillator mode of operation. 1 configure external oscillator for high gain operation 0 configure external oscillator for low power operation 3 lp low power select ? the lp bit controls whether the fl l is disabled in fll bypassed modes. 1 fll is disabled in bypass modes unless bdm is active 0 fll is not disabled in bypass mode 2 erefs external reference select ? the erefs bit selects the source for the external reference clock. 1 oscillator requested 0 external clock source requested 1 erclken external reference enable ? the erclken bit enables the external reference clock for use as icserclk. 1icserclk active 0 icserclk inactive 0 erefsten external reference stop enable ? the erefsten bit controls whether or not the external reference clock remains enabled when the ics enters stop mode. 1 external reference clock stays enabled in stop if erclken is set or if ics is in fee, fbe, or fbelp mode before entering stop 0 external reference clock is disabled in stop
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 122 freescale semiconductor 8.3.3 ics trim register (icstrm) 8.3.4 ics status and control (icssc) 7 6543210 r trim w por: 1 0 0 0 0 0 0 0 r e s e t :u uuuuuuu figure 8-5. ics trim register (icstrm) table 8-4. ics trim register field descriptions field description 7:0 trim ics trim setting ? the trim bits control the internal reference clock frequency by controlling the internal reference clock period. the bits? effect are binary weig hted (i.e., bit 1 will adjust twice as much as bit 0). increasing the binary value in trim will increase the period, and decreasing the value will decrease the period. an additional fine trim bit is available in icssc as the ftrim bit. 7 6543210 r 0 0 0 irefst clkst oscinit ftrim w por: reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 u figure 8-6. ics status and control register (icssc) table 8-5. ics status and control register field descriptions field description 7:5 reserved, should be cleared. 4 irefst internal reference status ? the irefst bit indicates the current s ource for the reference clock. the irefst bit does not update immediately after a write to the irefs bit due to internal synchronization between clock domains. 0 source of reference clock is external clock. 1 source of reference clock is internal clock. 3-2 clkst clock mode status ? the clkst bits indicate the current clock mode. the clkst bits don?t update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 output of fll is selected. 01 fll bypassed, internal reference clock is selected. 10 fll bypassed, external re ference clock is selected. 11 reserved.
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 123 8.4 functional description 8.4.1 operational modes figure 8-7. clock switching modes the seven states of the ics are show n as a state diagram and are describe d below. the arrows indicate the allowed movements between the states. 8.4.1.1 fll engaged internal (fei) fll engaged internal (fei) is the default mode of operation and is entered when all the following conditions occur: 1 osc initialization ? if the external reference clock is selected by erclken or by the ics being in fee, fbe, or fbelp mode, and if erefs is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. this bit is only cleared when either erclken or erefs are cleared. 0 ics fine trim ? the ftrim bit controls the sm allest adjustment of the inte rnal reference clock frequency. setting ftrim will increase the period and clearing ftrim will decrease the period by the smallest amount possible. table 8-5. ics status and control register field descriptions (continued) field description fll bypassed internal low power(fbilp) irefs=1 clks=00 entered from any state when mcu enters stop fll engaged internal (fei) fll bypassed internal (fbi) fll bypassed external (fbe) fll engaged external (fee) fll bypassed external low power(fbelp) irefs=0 clks=00 irefs=0 clks=10 bdm enabled or lp =0 returns to state that was active before mcu entered stop, unless reset occurs while in stop. irefs=0 clks=10 bdm disabled and lp=1 irefs=1 clks=01 bdm enabled or lp=0 irefs=1 clks=01 bdm disabled and lp=1 stop
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 124 freescale semiconductor ? clks bits are written to 00 ? irefs bit is written to 1 ? rdiv bits are written to divide trimmed reference clock to be within the range of 31.25 khz to 39.0625 khz. in fll engaged internal mode, the icsout clock is derived from th e fll clock, which is controlled by the internal reference clock. the fll loop will lock the frequency to 1024 times the reference frequency, as selected by the rdiv bits. the icslclk is av ailable for bdc communications, and the internal reference clock is enabled. 8.4.1.2 fll engaged external (fee) the fll engaged external (fee) mode is ente red when all the following conditions occur: ? clks bits are written to 00 ? irefs bit is written to 0 ? rdiv bits are written to divide reference clock to be within the range of 31.25 khz to 39.0625 khz in fll engaged external mode, the icsout clock is derived from the fll clock which is controlled by the external reference clock.the fll loop will lock the frequency to 1024 times the reference frequency, as selected by the rdiv bits. the icslclk is av ailable for bdc communications, and the external reference clock is enabled. 8.4.1.3 fll bypassed internal (fbi) the fll bypassed internal (fbi) mode is entered when all the following conditions occur: ? clks bits are written to 01 ? irefs bit is written to 1. ? bdm mode is active or lp bit is written to 0 in fll bypassed internal mode, the icsout clock is derived from the internal reference clock. the fll clock is controlled by the internal reference clock, and the fll loop will lock the fll frequency to 1024 times the reference frequency, as selected by the rdiv bits. the icslclk wi ll be available for bdc communications, and the internal reference clock is enabled. 8.4.1.4 fll bypassed internal low power (fbilp) the fll bypassed internal low power (fbilp) mode is entered when all the following conditions occur: ? clks bits are written to 01 ? irefs bit is written to 1. ? bdm mode is not active and lp bit is written to 1 in fll bypassed internal low power m ode, the icsout clock is derived from the internal reference clock and the fll is disabled. the icslcl k will be not be avai lable for bdc communicat ions, and the internal reference clock is enabled.
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 125 8.4.1.5 fll bypassed external (fbe) the fll bypassed external (fbe) mode is ente red when all the following conditions occur: ? clks bits are written to 10. ? irefs bit is written to 0. ? bdm mode is active or lp bit is written to 0. in fll bypassed external mode, the ic sout clock is derived from the external reference clock. the fll clock is controlled by the external reference clock, and the fll loop will lock the fll frequency to 1024 times the reference frequency, as se lected by the rdiv bits, so that the icslclk will be available for bdc communications, and the extern al reference clock is enabled. 8.4.1.6 fll bypassed external low power (fbelp) the fll bypassed external lo w power (fbelp) mode is entered when all the following conditions occur: ? clks bits are written to 10. ? irefs bit is written to 0. ? bdm mode is not active and lp bit is written to 1. in fll bypassed external low power mode, the icsout clock is derived from the external reference clock and the fll is disabled. the icsl clk will be not be available fo r bdc communications. the external reference clock is enabled. 8.4.1.7 stop stop mode is entered whenever the mc u enters a stop state. in this m ode, all ics clock si gnals are static except in the following cases: icsirclk will be active in stop mode when all the following conditions occur: ? irclken bit is written to 1 ? irefsten bit is written to 1 icserclk will be active in stop mode when all the following conditions occur: ? erclken bit is written to 1 ? erefsten bit is written to 1 8.4.2 mode switching when switching between fll engage d internal (fei) and fll engaged external (fee) modes the irefs bit can be changed at anytime, but the rdiv bits must be changed simultaneously so that the resulting frequency stays in the range of 3 1.25 khz to 39.0625 khz. after a change in the irefs value the fll will begin locking again after a few full cycles of the re sulting divided reference frequency. the completion of the switch is shown by the irefst bit.
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 126 freescale semiconductor the clks bits can also be changed at anytime, but the rdiv bits mu st be changed simultaneously so that the resulting frequency stays in the range of 31.25 khz to 39.0625 khz. the actual switch to the newly selected clock will not occur until afte r a few full cycles of the new cloc k. if the newly selected clock is not available, the previous clock will remain selected. 8.4.3 bus frequency divider the bdiv bits can be changed at anytime and th e actual switch to the new frequency will occur immediately. 8.4.4 low power bit usage the low power bit (lp) is provided to allow the fll to be disabled and thus conserve power when it is not being used. however, in some app lications it may be desirable to enable the fll and allow it to lock for maximum accuracy before switching to an fll e ngaged mode. do this by writing the lp bit to 0. 8.4.5 internal reference clock when irclken is set the internal reference clock signal will be presented as ic sirclk, which can be used as an additional clock source. the icsirclk frequency can be re-targe ted by trimming the period of the internal reference clock. this can be done by writing a new value to the trim bits in the icstrm register. writing a larger value will slow down the icsirclk frequency, and wr iting a smaller value to the icstrm register will speed up the icsirclk fr equency. the trim bits will effect the icsout frequency if the ics is in fll engaged internal (fei), fll bypassed internal (fbi), or fll bypassed internal low power (fbilp) mode. the trim and ftrim value will not be affected by a reset. until icsirclk is trimmed, programm ing low reference divider (rdiv) factors may result in icsout frequencies that exceed the maxi mum chip-level frequency and viol ate the chip-level clock timing specifications (see the device overview chapter). if irefsten is set and the irclken bit is written to 1, the internal refere nce clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. all mcu devices are factor y programmed with a trim value in a rese rved memory location. this value can be copied to the icstrm register during reset init ialization. the factory trim value does not include the ftrim bit. for finer precision, the us er can trim the internal oscillat or in the application and set the ftrim bit accordingly. 8.4.6 optional external reference clock the ics module can support an exte rnal reference clock with freq uencies between 31.25 khz to 5 mhz in all modes. when the erclken is set, the exte rnal reference clock signa l will be presented as icserclk, which can be used as an additional cloc k source. when irefs = 1, the external reference clock will not be used by the fll and will only be used as icserclk. in these modes, the frequency can be equal to the maximum frequency the chip-lev el timing specifications will support (see the device overview chapter).
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 127 if erefsten is set and the erclken bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 8.4.7 fixed frequency clock the ics presents the divided fll re ference clock as icsffclk for use as an additional clock source for peripheral modules. the ics provide s an output signal (icsffe) whic h indicates when the ics is providing icsout frequencies four times or greater than the divided fll reference clock (icsffclk). in fll engaged mode (fei and fee) this is alwa ys true and icsffe is always high. in ics bypass modes, icsffe will get asserted for the follow ing combinations of bdiv and rdiv values: ? bdiv=00 (divide by 1), rdiv 010 ? bdiv=01 (divide by 2), rdiv 011 ? bdiv=10 (divide by 4), rdiv 100 ? bdiv=11 (divide by 8), rdiv 101
internal clock source (s08icsv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 128 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 129 chapter 9 5-v analog comparator (s08acmpv2) 9.1 introduction the analog comparator module (acmp) provides a circuit fo r comparing two analog input voltages or for comparing one analog input voltage to an internal refe rence voltage. the comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). all mc9s08el32 series and mc9s08sl16 series mc us contain at least one acmp. mc9s08el32 and mc9s08el16 contain two acmps in the 28-pin package. see table 9-1 . t note the mc9s08el32 series and mc9s08sl16 series family of devices operates at a higher voltage range (2.7 v to 5.5 v) and does not include stop1 mode. 9.1.1 acmpx configuration information when using the bandgap reference voltage for input to acmpx+, the user must enable the bandgap buffer by setting bgbe =1 in spmsc1 see section 5.7.6, ?system power manage ment status and control 1 register (spmsc1) ?. for value of bandgap voltage reference see section a.6, ?dc characteristics ?. 9.1.2 acmp1/tpm1 configuration information the acmp1 module can be configured to connect th e output of the analog comparator to tpm1 input capture channel 0 by setting acic in sopt2. with acic set, the tpm1ch0 pin is not available externally regardless of the configuration of the tpm1 module for channel 0. table 9-1. mc9s08el32 series and mc9s08sl16 series features by mcu and package feature 9s08el32 9s08el16 9s08sl16 9s08sl8 pin quantity 2820282028202820 package type tssop tssop tssop tssop tssop tssop tssop tssop acmp1 yes yes acmp2 yes no yes no no
chapter 9 5-v analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 130 freescale semiconductor figure 9-1. mc9s08el32 block diagram highlighting acmp block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 131 9.1.3 features the acmp has the following features: ? full rail to ra il supply operation. ? selectable interrupt on rising edge , falling edge, or either rising or falling edges of comparator output. ? option to compare to fixed internal bandgap reference voltage. ? option to allow comparator outpu t to be visible on a pin, acmpxo. ? can operate in stop3 mode 9.1.4 modes of operation this section defines the acmp operatio n in wait, stop and background debug modes. 9.1.4.1 acmp in wait mode the acmp continues to run in wait mode if enable d before executing the wait instruction. therefore, the acmp can be used to bring the mcu out of wait mode if the acmp interrupt, acie is enabled. for lowest possible current consumption, the acmp should be disabled by software if not required as an interrupt source during wait mode. 9.1.4.2 acmp in stop modes 9.1.4.2.1 stop3 mode operation the acmp continues to operate in stop3 mode if enabled and compare operation remains active. if acope is enabled, comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. the mcu is brought out of stop when a compare event occurs and acie is enabled; acf flag sets accordingly. if stop is exited with a reset, the ac mp will be put into its reset state. 9.1.4.2.2 stop2 and st op1 mode operation during either stop2 and stop1 mode, the acmp module will be fully powered down. upon wake-up from stop2 or stop1 mode, the acmp modul e will be in the reset state. 9.1.4.3 acmp in active background mode when the microcontroller is in ac tive background mode, the acmp wi ll continue to operate normally.
analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 132 freescale semiconductor 9.1.5 block diagram the block diagram for the anal og comparator module is shown figure 9-2 . figure 9-2. analog comparator 5v (acmp5) block diagram + - interrupt control internal reference acbgs internal bus status & control register acmod set acf acme acf acie acope comparator acmpx interrupt request acmpx+ acmpx- acmpxo
analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 133 9.2 external signal description the acmp has two analog input pi ns, acmpx+ and acmpx- and one digital output pin acmpxo. each of these pins can accept an input vol tage that varies across the full operating voltage range of the mcu. as shown in figure 9-2 , the acmpx- pin is connected to the i nverting input of the comparator, and the acmpx+ pin is connected to the comparator non- inverting input if acbg s is a 0. as shown in figure 9-2 , the acmpxo pin can be enabled to drive an external pin. the signal properties of acmp are shown in table 9-2 . 9.3 memory map 9.3.1 register descriptions the acmp includes one register: ? an 8-bit status and control register refer to the direct-page register summ ary in the memory section of this data sheet for the absolute address assignments for all acmp registers.th is section refers to registers a nd control bits only by their names . some mcus may have more than one acmp, so regist er names include placeholde r characters to identify which acmp is being referenced. table 9-2. signal properties signal function i/o acmpx- inverting analog input to the acmp. (minus input) i acmpx+ non-inverting analog input to the acmp. (positive input) i acmpxo digital output of the acmp. o
analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 134 freescale semiconductor 9.3.1.1 acmpx status and c ontrol register (acmpxsc) acmpxsc contains the status flag and control bits which are used to enable and configure the acmp. 76543210 r acme acbgs acf acie aco acope acmod w r e s e t :00000000 = unimplemented figure 9-3. acmpx status and control register table 9-3. acmpx status and cont rol register field descriptions field description 7 acme analog comparator module enable ? acme enables the acmp module. 0 acmp not enabled 1 acmp is enabled 6 acbgs analog comparator bandgap select ? acbgs is used to select between the bandgap reference voltage or the acmpx+ pin as the input to the non- inverting input of the analog comparatorr. 0 external pin acmpx+ selected as non-inverting input to comparator 1 internal reference select as non-inverting input to comparator note: refer to this chapter introduction to verify if any other config bits are necessary to enable the bandgap reference in the chip level. 5 acf analog comparator flag ? acf is set when a compare event occu rs. compare events are defined by acmod. acf is cleared by writing a one to acf. 0 compare event has not occured 1 compare event has occured 4 acie analog comparator interrupt enable ? acie enables the interrupt from the acmp. when acie is set, an interupt will be asserted when acf is set. 0 interrupt disabled 1 interrupt enabled 3 aco analog comparator output ? reading aco will return the current value of the analog comparator output. aco is reset to a 0 and will read as a 0 when the acmp is disabled (acme = 0). 2 acope analog comparator output pin enable ? acope is used to enable the comparator output to be placed onto the external pin, acmpxo. 0 analog comparator output not available on acmpxo 1 analog comparator output is driven out on acmpxo 1:0 acmod analog comparator mode ? acmod selects the type of co mpare event which sets acf. 00 encoding 0 ? comparator output falling edge 01 encoding 1 ? comparator output rising edge 10 encoding 2 ? comparator output falling edge 11 encoding 3 ? comparator output rising or falling edge
analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 135 9.4 functional description the analog comparator can be used to compare two analog input voltages applied to acmpx+ and acmpx-; or it can be used to compare an analog i nput voltage applied to acmpx- with an internal bandgap reference voltage. acbgs is used to select between the ba ndgap reference voltage or the acmpx+ pin as the input to the non- inverting input of the analog comparator. the comparator output is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. acmod is used to select the condition whic h will cause acf to be set. acf can be set on a ri sing edge of the comparator output, a falling edge of the comparator output, or either a rising or a falling edge (toggle). the comparator output can be read directly through aco. the comparator output can be driven onto the acmpxo pin using acope.
analog comparator (s08acmpv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 136 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 137 chapter 10 analog-to-digital converter (s08adcv1) 10.1 introduction the 10-bit analog-to-digital convert er (adc) is a successive appr oximation adc desi gned for operation within an integrated microcontroller system-on-chip. note mc9s08el32 series and mc9s08sl16 se ries devices opera tes at a higher voltage range (2.7 v to 5.5 v) and does not include stop1 mode. the adc channel assignments, alternat e clock function, and hardware tr igger function are configured as described below for the mc9s08el32 series and mc9s08sl16 series family of devices. 10.1.1 channel assignments the adc channel assignments for the mc9s08el32 series and mc9s08s l16 series devices are shown in table 10-1 . reserved channels conve rt to an unknown value. table 10-1. adc channel assignment adch channel input adch channel input 00000 ad0 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 10000 ad16 v refl 00001 ad1 pta1/pia1/tpm2 ch0/acmp1-/adp1 10001 ad17 v refl 00010 ad2 pta2/pia2/sda/r xd/acmp1o/adp2 10010 ad18 v refl 00011 ad3 pta3/pia3/scl/txd/adp3 10011 ad19 v refl 00100 ad4 ptb0/pib0/slrxd/rxd/adp4 10100 ad20 v refl 00101 ad5 ptb1/pib1/sltxd/txd/adp5 10101 ad21 v refl 00110 ad6 ptb2/pib2/sda /spsck/adp6 10110 ad22 v refl 00111 ad7 ptb3/pib3/scl/mosi/adp7 10111 ad23 v refl 01000 ad8 ptc0/pic0/tpm1ch0/adp8 11000 ad24 reserved 01001 ad9 ptc1/pic1/tpm1ch1/adp9 11001 ad25 reserved 01010 ad10 ptc2/pic2/tpm1ch2/adp10 11010 ad26 temperature sensor 1 1 for information, see section 10.1.4, ?t emperature sensor ?. 01011 ad11 ptc3/pic3/tpm1ch3/adp11 11011 ad27 internal bandgap 2 2 requires bgbe =1 in spmsc1 see section 5.7.7, ?system power management status and control 2 register (spmsc2) ?. for value of bandgap voltage reference see section a.6, ?dc characteristics ?. 01100 ad12 ptc4/pic4/adp12 11100 v refh v refh 01101 ad13 ptc5/pic5/acmp2o/adp13 11101 v refh v refh 01110 ad14 ptc6/pic6/acmp2+/adp14 11110 v refl v refl 01111 ad15 ptc7/pic7/acmp2-/adp15 11111 module disabled none
chapter 10 analog-to-digital converter (s08adcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 138 freescale semiconductor 10.1.2 alternate clock the adc module is capable of perf orming conversions using the mcu bus clock, the bus clock divided by two, the local asynchronous clock (adack) within the module, or the alte rnate clock, altclk. the alternate clock for the mc9s08el32 series and mc9s08sl16 seri es mcu devices is the external reference clock (icserclk). the selected clock source mu st run at a frequency such that the adc conversion clock (adck) runs at a frequency within its specified range (f adck ) after being divided down fr om the altclk input as determined by the adiv bits. altclk is active while the mcu is in wait mode provided the conditi ons described above are met. this allows altclk to be used as the conversion clock source for the adc while the mcu is in wait mode. altclk cannot be used as the ad c conversion clock source while the mcu is in either stop2 or stop3. 10.1.3 hardware trigger the adc hardware trigger, adhwt, is the output from the real time counter (rtc) overflow. the rtc can be configured to cause a hardware trigger in mcu run, wait, and stop3 modes. 10.1.4 temperature sensor the adc module includes a temperature sensor whose output is connected to ad26. equation 10-1 provides an approximate transfer f unction of the temperature sensor. temp = 25 - ((v temp -v temp25 ) m) eqn. 10-1 where: ?v temp is the voltage of the temperature sens or channel at the ambient temperature. ?v temp25 is the voltage of the temperature sensor channel at 25 c. ? m is the hot or cold voltage versus temperature slope in v/ c. for temperature calculations, use the v temp25 and m values from the adc electricals table. in application code, the us er reads the temperature se nsor channel, calculates v temp , and compares to v temp25 . if v temp is greater than v temp25 the cold slope value is applied in equation 10-1 . if v temp is less than v temp25 the hot slope value is applied in equation 10-1 .
chapter 10 analog-to-digital converter (s08adcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 139 figure 10-1 shows the mc9s08el32 with the adc module highlighted. figure 10-1. mc9s08el32 block diagra m highlighting adc block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
chapter 10 analog-to-digital converter (s08adcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 140 freescale semiconductor
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 141 10.1.5 features features of the adc module include: ? linear successive approximation al gorithm with 10 bits resolution. ? up to 28 analog inputs. ? output formatted in 10- or 8-bit right-justified format. ? single or continuous conversion (automatic return to idle afte r single conversion). ? configurable sample time and conversion speed/power. ? conversion complete flag and interrupt. ? input clock selectable fr om up to four sources. ? operation in wait or stop3 m odes for lower noise operation. ? asynchronous clock source for lower noise operation. ? selectable asynchronous hardware conversion trigger. ? automatic compare with interrupt for less-than, or gr eater-than or equal-t o, programmable value. 10.1.6 block diagram figure 10-2 provides a block diagram of the adc module
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 142 freescale semiconductor figure 10-2. adc block diagram 10.2 external signal description the adc module supports up to 28 se parate analog inputs. it also re quires four supply/reference/ground connections. table 10-2. signal properties name function ad27?ad0 analog channel inputs v refh high reference voltage v refl low reference voltage v ddad analog power supply v ssad analog ground ad0 ? ? ? ad27 v refh v refl advin adch control sequencer initialize sample convert transfer abort clock divide adck 2 async clock gen bus clock altclk adiclk adiv adack adco adlsmp adlpc mode complete data registers sar converter compare value registers compare value sum aien coco interrupt aien coco adtrg 1 2 1 2 mcu stop adhwt logic acfgt 3 compare true 3 compare true adccfg adcsc1 adcsc2
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 143 10.2.1 analog power (v ddad ) the adc analog portion uses v ddad as its power connection. in some packages, v ddad is connected internally to v dd . if externally available, connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. 10.2.2 analog ground (v ssad ) the adc analog portion uses v ssad as its ground connection. in some packages, v ssad is connected internally to v ss . if externally available, connect the v ssad pin to the same voltage potential as v ss . 10.2.3 voltage reference high (v refh ) v refh is the high reference voltage for the converter . in some packages, v refh is connected internally to v ddad . if externally available, v refh may be connected to the same potential as v ddad , or may be driven by an external source th at is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). 10.2.4 voltage reference low (v refl ) v refl is the low reference voltage for the converter. in some packages, v refl is connected internally to v ssad . if externally available, connect the v refl pin to the same voltage potential as v ssad . 10.2.5 analog channel inputs (adx) the adc module supports up to 28 separate analog input s. an input is selected for conversion through the adch channel select bits. 10.3 register definition these memory mapped registers contro l and monitor operation of the adc: ? status and control register, adcsc1 ? status and control register, adcsc2 ? data result registers, adcrh and adcrl ? compare value registers, adccvh and adccvl ? configuration register, adccfg ? pin enable registers, apctl1, apctl2, apctl3 10.3.1 status and contro l register 1 (adcsc1) this section describes the functi on of the adc status and control register (adcsc1). writing adcsc1 aborts the current c onversion and initiates a new c onversion (if the adch bits are equal to a value other than all 1s).
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 144 freescale semiconductor 7654 3 210 rcoco aien adco adch w r e s e t :0001 1 111 = unimplemented or reserved figure 10-3. status and control register (adcsc1) table 10-3. adcsc1 register field descriptions field description 7 coco conversion co mplete flag ? the coco flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (acfe = 0). when the compare function is enabled (acfe = 1) the coco flag is set upon completion of a conversion only if the compare result is true. this bit is cleared whenever adcsc1 is written or whenever adcrl is read. 0 conversion not completed 1 conversion completed 6 aien interrupt enable ? aien is used to enable conversion comp lete interrupts. when coco becomes set while aien is high, an interrupt is asserted. 0 conversion complete interrupt disabled 1 conversion complete interrupt enabled 5 adco continuous conversion enable ? adco is used to enable continuous conversions. 0 one conversion following a write to the adcsc1 when software triggered operation is selected, or one conversion following assertion of adhwt when hardware triggered operation is selected. 1 continuous conversions initiated following a write to adcsc1 when software triggered operation is selected. continuous conversions are initiated by an adhwt event when hardware triggered operation is selected. 4:0 adch input channel select ? the adch bits form a 5-bit field which is used to select one of the input channels. the input channels are detailed in figure 10-4 . the successive approximation converter subsystem is turned off when the channel select bits are all set to 1. this feature allows for explicit di sabling of the adc and isolation of the input channel from all sources. terminating continuous conversions this way will prevent an additional, single conversion from being performed. it is not necessary to set the channel select bits to all 1s to place the adc in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. figure 10-4. input channel select adch input select adch input select 00000 ad0 10000 ad16 00001 ad1 10001 ad17 00010 ad2 10010 ad18 00011 ad3 10011 ad19 00100 ad4 10100 ad20 00101 ad5 10101 ad21 00110 ad6 10110 ad22 00111 ad7 10111 ad23
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 145 10.3.2 status and contro l register 2 (adcsc2) the adcsc2 register is used to control the compare function, convers ion trigger and conversion active of the adc module. figure 10-5. status and control register 2 (adcsc2) 01000 ad8 11000 ad24 01001 ad9 11001 ad25 01010 ad10 11010 ad26 01011 ad11 11011 ad27 01100 ad12 11100 reserved 01101 ad13 11101 v refh 01110 ad14 11110 v refl 01111 ad15 11111 module disabled 7654 3 210 radact adtrg acfe acfgt 00 r 1 1 bits 1 and 0 are reserved bits that must always be written to 0. r 1 w r e s e t :0000 0 000 = unimplemented or reserved table 10-4. adcsc2 register field descriptions field description 7 adact conversion active ? adact indicates that a conversion is in progress. adact is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 conversion not in progress 1 conversion in progress 6 adtrg conversion trigger select ? adtrg is used to select the type of trigger to be used for initiating a conversion. two types of trigger are selectable: software trigger a nd hardware trigger. when software trigger is selected, a conversion is initiated following a write to adcsc1. when hardware trigger is selected, a conversion is initiated following the assertion of the adhwt input. 0 software trigger selected 1 hardware trigger selected figure 10-4. input channel select (continued) adch input select adch input select
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 146 freescale semiconductor 10.3.3 data result hi gh register (adcrh) adcrh contains the upper two bits of the result of a 10-bit conversion. when configured for 8-bit conversions both adr8 and adr9 are equal to zero. adcrh is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is rea d. if adcrl is not read unt il after the next conversi on is completed, then the intermediate conversion result will be lost. in 8-bit mode there is no interlocking with adcrl. in the case that the mode bits are changed, a ny data in adcrh becomes invalid. 10.3.4 data result low register (adcrl) adcrl contains the lower eight bits of the result of a 10-bit conversi on, and all eight bits of an 8-bit conversion. this register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, readi ng adcrh prevents the adc from transferring subsequent conversion results into the result registers unt il adcrl is read. if adcrl is not read until the after next conversion is completed, then the intermediate conversion results will be lost. in 8-bit mode, there is no interlocking with adcrh. in the case that the mode bits are changed, any data in adcrl becomes invalid. 5 acfe compare function enable ? acfe is used to enable the compare function. 0 compare function disabled 1 compare function enabled 4 acfgt compare function greater than enable ? acfgt is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. the compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 compare triggers when input is less than compare level 1 compare triggers when input is greater than or equal to compare level 7 6543210 r 0 0 0 0 0 0 adr9 adr8 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 10-6. data result high register (adcrh) table 10-4. adcsc2 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 147 10.3.5 compare value high register (adccvh) this register holds the upper two bits of the 10-bit compare value. these bits are compared to the upper two bits of the result following a conversion in 10-bi t mode when the compare function is enabled.in 8-bit operation, adccvh is not used during compare. 10.3.6 compare value low register (adccvl) this register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value. bits adcv7:adcv0 are compared to th e lower 8 bits of the result following a conve rsion in either 10-bit or 8-bit mode. 10.3.7 configuration register (adccfg) adccfg is used to select the mode of operation, cloc k source, clock divide, a nd configure for low power or long sample time. 7 6543210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 10-7. data resu lt low register (adcrl) 7654 3 210 r0 0 0 0 adcv9 adcv8 w r e s e t :0000 0 000 = unimplemented or reserved figure 10-8. compare value high register (adccvh) 7 6543210 r adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 w reset: 0 0 0 0 0 0 0 0 figure 10-9. compare value low register(adccvl)
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 148 freescale semiconductor 7654 3 210 r adlpc adiv adlsmp mode adiclk w r e s e t :0000 0 000 figure 10-10. c onfiguration re gister (adccfg) table 10-5. adccfg regist er field descriptions field description 7 adlpc low power configuration ? adlpc controls the speed and po wer configuration of the successive approximation converter. this is used to optimize powe r consumption when higher sample rates are not required. 0 high speed configuration 1 low power configuration: {fc31}the power is reduced at the expense of maximum clock speed. 6:5 adiv clock divide select ? adiv select the divide ratio used by the adc to generate the internal clock adck. ta b l e 1 0 - 6 shows the available clock configurations. 4 adlsmp long sample time configuration ? adlsmp selects between long and short sample time. this adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if hi gh conversion rates are not required. 0 short sample time 1 long sample time 3:2 mode conversion mode selection ? mode bits are used to select between 10- or 8-bit operation. see table 10-7 . 1:0 adiclk input clock select ? adiclk bits select the input clock source to generate the internal clock adck. see ta b l e 1 0 - 8 . table 10-6. clock divide select adiv divide ratio clock rate 00 1 input clock 01 2 input clock 2 10 4 input clock 4 11 8 input clock 8 table 10-7. conversion modes mode mode description 00 8-bit conversion (n=8) 01 reserved 10 10-bit conversion (n=10) 11 reserved
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 149 10.3.8 pin control 1 register (apctl1) the pin control registers are used to disable the i/ o port control of mcu pins used as analog inputs. apctl1 is used to control the pins asso ciated with channels 0?7 of the adc module. table 10-8. input clock select adiclk selected clock source 00 bus clock 01 bus clock divided by 2 10 alternate clock (altclk) 11 asynchronous clock (adack) 7654 3 210 r adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 w r e s e t :0000 0 000 figure 10-11. pin control 1 register (apctl1) table 10-9. apctl1 register field descriptions field description 7 adpc7 adc pin control 7 ? adpc7 is used to control the pin associated with channel ad7. 0 ad7 pin i/o control enabled 1 ad7 pin i/o control disabled 6 adpc6 adc pin control 6 ? adpc6 is used to control the pin associated with channel ad6. 0 ad6 pin i/o control enabled 1 ad6 pin i/o control disabled 5 adpc5 adc pin control 5 ? adpc5 is used to control the pin associated with channel ad5. 0 ad5 pin i/o control enabled 1 ad5 pin i/o control disabled 4 adpc4 adc pin control 4 ? adpc4 is used to control the pin associated with channel ad4. 0 ad4 pin i/o control enabled 1 ad4 pin i/o control disabled 3 adpc3 adc pin control 3 ? adpc3 is used to control the pin associated with channel ad3. 0 ad3 pin i/o control enabled 1 ad3 pin i/o control disabled 2 adpc2 adc pin control 2 ? adpc2 is used to control the pin associated with channel ad2. 0 ad2 pin i/o control enabled 1 ad2 pin i/o control disabled
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 150 freescale semiconductor 10.3.9 pin control 2 register (apctl2) apctl2 is used to control ch annels 8?15 of the adc module. 1 adpc1 adc pin control 1 ? adpc1 is used to control the pin associated with channel ad1. 0 ad1 pin i/o control enabled 1 ad1 pin i/o control disabled 0 adpc0 adc pin control 0 ? adpc0 is used to control the pin associated with channel ad0. 0 ad0 pin i/o control enabled 1 ad0 pin i/o control disabled 7654 3 210 r adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 w reset:0000 0 000 figure 10-12. pin control 2 register (apctl2) table 10-10. apctl2 register field descriptions field description 7 adpc15 adc pin control 15 ? adpc15 is used to control the pin associated with channel ad15. 0 ad15 pin i/o control enabled 1 ad15 pin i/o control disabled 6 adpc14 adc pin control 14 ? adpc14 is used to control the pin associated with channel ad14. 0 ad14 pin i/o control enabled 1 ad14 pin i/o control disabled 5 adpc13 adc pin control 13 ? adpc13 is used to control the pin associated with channel ad13. 0 ad13 pin i/o control enabled 1 ad13 pin i/o control disabled 4 adpc12 adc pin control 12 ? adpc12 is used to control the pin associated with channel ad12. 0 ad12 pin i/o control enabled 1 ad12 pin i/o control disabled 3 adpc11 adc pin control 11 ? adpc11 is used to control the pin associated with channel ad11. 0 ad11 pin i/o control enabled 1 ad11 pin i/o control disabled 2 adpc10 adc pin control 10 ? adpc10 is used to control the pin associated with channel ad10. 0 ad10 pin i/o control enabled 1 ad10 pin i/o control disabled table 10-9. apctl1 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 151 10.3.10 pin control 3 register (apctl3) apctl3 is used to control ch annels 16?23 of the adc module. 1 adpc9 adc pin control 9 ? adpc9 is used to control the pin associated with channel ad9. 0 ad9 pin i/o control enabled 1 ad9 pin i/o control disabled 0 adpc8 adc pin control 8 ? adpc8 is used to control the pin associated with channel ad8. 0 ad8 pin i/o control enabled 1 ad8 pin i/o control disabled 7654 3 210 r adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 w reset:0000 0 000 figure 10-13. pin control 3 register (apctl3) table 10-11. apctl3 register field descriptions field description 7 adpc23 adc pin control 23 ? adpc23 is used to control the pin associated with channel ad23. 0 ad23 pin i/o control enabled 1 ad23 pin i/o control disabled 6 adpc22 adc pin control 22 ? adpc22 is used to control the pin associated with channel ad22. 0 ad22 pin i/o control enabled 1 ad22 pin i/o control disabled 5 adpc21 adc pin control 21 ? adpc21 is used to control the pin associated with channel ad21. 0 ad21 pin i/o control enabled 1 ad21 pin i/o control disabled 4 adpc20 adc pin control 20 ? adpc20 is used to control the pin associated with channel ad20. 0 ad20 pin i/o control enabled 1 ad20 pin i/o control disabled 3 adpc19 adc pin control 19 ? adpc19 is used to control the pin associated with channel ad19. 0 ad19 pin i/o control enabled 1 ad19 pin i/o control disabled 2 adpc18 adc pin control 18 ? adpc18 is used to control the pin associated with channel ad18. 0 ad18 pin i/o control enabled 1 ad18 pin i/o control disabled table 10-10. apctl2 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 152 freescale semiconductor 10.4 functional description the adc module is disabled during re set or when the adch bits are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when idle, the module is in its lowest power state. the adc can perform an analog-to- digital conversion on any of the so ftware selectable channels. the selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result. in 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. when the conversion is completed, the result is pl aced in the data registers (adcrh and adcrl).in 10-bit mode, the result is rounded to 10 bits and pl aced in adcrh and adcrl. in 8-bit mode, the result is rounded to 8 bits and placed in adcrl. the c onversion complete flag (coco) is then set and an interrupt is generated if the conversion comp lete interrupt has been enabled (aien = 1). the adc module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. the compare f unction is enabled by setting the acfe bit and operates in conjunction with any of the c onversion modes and configurations. 10.4.1 clock select and divide control one of four clock sources can be selected as the cl ock source for the adc module. this clock source is then divided by a configurable valu e to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. ? the bus clock, which is e qual to the frequency at which software is executed. this is the default selection following reset. ? the bus clock divided by 2. for hi gher bus clock rates, this allows a maximum divide by 16 of the bus clock. ? altclk, as defined for this mc u (see module section introduction). ? the asynchronous clock (adack) ? this clock is generated from a clock source within the adc module. when selected as the clock source this clock remains active while the mcu is in wait or stop3 mode and allows conversions in these modes for lower noise operation. whichever clock is selecte d, its frequency must fall within the specified freque ncy range for adck. if the available clocks are too sl ow, the adc will not perform according to specifications. if th e available clocks 1 adpc17 adc pin control 17 ? adpc17 is used to control the pin associated with channel ad17. 0 ad17 pin i/o control enabled 1 ad17 pin i/o control disabled 0 adpc16 adc pin control 16 ? adpc16 is used to control the pin associated with channel ad16. 0 ad16 pin i/o control enabled 1 ad16 pin i/o control disabled table 10-11. apctl3 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 153 are too fast, then the clock must be divided to the appropriate frequency. this divider is specified by the adiv bits and can be divide-by 1, 2, 4, or 8. 10.4.2 input select and pin control the pin control registers (apctl3, ap ctl2, and apctl1) are used to di sable the i/o port control of the pins used as analog inputs.when a pi n control register bit is set, the following conditions ar e forced for the associated mcu pin: ? the output buffer is forced to its high impedance state. ? the input buffer is disabled. a read of the i/o port returns a zero for any pin with its input buffer disabled. ? the pullup is disabled. 10.4.3 hardware trigger the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set. this source is not available on all mcus . consult the module introduction for information on the adhwt sour ce specific to this mcu. when adhwt source is available and hardware trigger is enabled (adt rg=1), a conversion is initiated on the rising edge of adhwt. if a conversion is in progr ess when a rising edge oc curs, the rising edge is ignored. in continuous convert confi guration, only the initial rising edge to launch continuous conversions is observed. the hardware trigger function operates in conjunction with any of the conversion modes and configurations. 10.4.4 conversion control conversions can be performed in ei ther 10-bit mode or 8-bit mode as determined by the mode bits. conversions can be initiated by either a software or hardwa re trigger. in addition, the adc module can be configured for low power operation, long sample time, continuous conve rsion, and automatic compare of the conversion result to a soft ware determined compare value. 10.4.4.1 initiating conversions a conversion is initiated: ? following a write to adcsc1 (wit h adch bits not all 1s) if so ftware triggered operation is selected. ? following a hardware trigger (adhwt) event if hardware triggered operation is selected. ? following the transfer of the result to the data registers when continuous conversion is enabled. if continuous conversions are enable d a new conversion is automatically initiated after the completion of the current conversion. in software triggered operation, continuous conversions begin after adcsc1 is written and continue until aborted. in hardware triggered operation, continuous conversions begin after a hardware trigger event a nd continue until aborted.
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 154 freescale semiconductor 10.4.4.2 completing conversions a conversion is completed when the result of the convers ion is transferred into th e data result registers, adcrh and adcrl. this is indicated by the setting of coco. an interr upt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a new result from overwriting previous data in adcrh and adcrl if the previous data is in th e process of being read while in 10-bit mo de (the adcrh register has been read but the adcrl register has not). when blocking is ac tive, the data transfer is blocked, coco is not set, and the new result is lost. in the case of single conversions with the compar e function enabled and the compare condition false, blocking ha s no effect and adc operation is te rminated. in all other cases of operation, when a data transfer is bl ocked, another conversion is initiated regardless of the state of adco (single or continuous conversions enabled). if single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. to avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 10.4.4.3 aborting conversions any conversion in progress will be aborted when: ? a write to adcsc1 occurs (the current convers ion will be aborted and a new conversion will be initiated, if adch are not all 1s). ? a write to adcsc2, adccfg, adccvh, or adccvl occurs. this indicates a mode of operation change has occurred and the current conversion is therefore invalid. ? the mcu is reset. ? the mcu enters stop mode with adack not enabled. when a conversion is aborted, the c ontents of the data registers, ad crh and adcrl, are not altered but continue to be the values transferred after the completi on of the last successful c onversion. in the case that the conversion was aborted by a reset, adcrh and adcrl return to their reset states. 10.4.4.4 power control the adc module remains in its idle st ate until a convers ion is initiated. if adack is selected as the conversion clock source, the adack clock generator is also enabled. power consumption when active can be reduced by se tting adlpc. this results in a lower maximum value for f adck (see the electrical specifications). 10.4.4.5 total conversion time the total conversion time depends on the sample time (as determined by adlsmp), the mcu bus frequency, the conversion mode (8-bit or 10-bi t), and the frequency of the conversion clock ( f adck ). after the module becomes active, sampling of the input begi ns. adlsmp is used to select between short and long sample times.when samp ling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digita l value of the analog signal. the
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 155 result of the conversion is transferred to adcrh and adcrl upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample ti me for continuous conversions cannot be guaranteed when s hort sample is enabled (a dlsmp=0). if the bus freque ncy is less than 1/11th of the f adck frequency, precise sample ti me for continuous conversions cannot be guaranteed when long sample is enabled (adlsmp=1). the maximum total conversion time for di fferent conditions is summarized in table 10-12 . the maximum total conversion time is determined by the clock source chosen and th e divide ratio selected. the clock source is selectable by th e adiclk bits, and the divide ratio is specified by the adiv bits. for example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, th en the conversion time for a single conversion is: note the adck frequency must be between f adck minimum and f adck maximum to meet adc specifications. table 10-12. total conversion time vs. control conditions conversion type adiclk adlsmp m ax total conversion time single or first continuous 8-bit 0x, 10 0 20 adck cycles + 5 bus clock cycles single or first continuous 10-bit 0x, 10 0 23 adck cycles + 5 bus clock cycles single or first continuous 8-bit 0x, 10 1 40 adck cycles + 5 bus clock cycles single or first continuous 10-bit 0x, 10 1 43 adck cycles + 5 bus clock cycles single or first continuous 8-bit 11 0 5 s + 20 adck + 5 bus clock cycles single or first continuous 10-bit 11 0 5 s + 23 adck + 5 bus clock cycles single or first continuous 8-bit 11 1 5 s + 40 adck + 5 bus clock cycles single or first continuous 10-bit 11 1 5 s + 43 adck + 5 bus clock cycles subsequent continuous 8-bit; f bus > f adck xx 0 17 adck cycles subsequent continuous 10-bit; f bus > f adck xx 0 20 adck cycles subsequent continuous 8-bit; f bus > f adck /11 xx 1 37 adck cycles subsequent continuous 10-bit; f bus > f adck /11 xx 1 40 adck cycles 23 adck cyc conversion time = 8 mhz/1 number of bus cycles = 3.5 s x 8 mhz = 28 cycles 5 bus cyc 8 mhz + = 3.5 s
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 156 freescale semiconductor 10.4.5 automatic compare function the compare function can be configur ed to check for either an upper li mit or lower limit . after the input is sampled and converted, the result is added to th e two?s complement of the compare value (adccvh and adccvl). when comparing to an upper limit (acfgt = 1), if the re sult is greater-t han or equal-to the compare value, coco is set. when comparing to a lower limit (acfgt = 0), if the result is less than the compare value, coco is set. th e value generated by the addition of the conversion result and the two?s complement of the compare value is transferred to adcrh and adcrl. upon completion of a conversion while the compare f unction is enabled, if the compare condition is not true, coco is not set and no data is transferred to the result register s. an adc interrupt is generated upon the setting of coco if the adc interrupt is enabled (aien = 1). note the compare function can be used to monitor the voltage on a channel while the mcu is in either wait or stop3 mode. the adc interrupt will wake the mcu when the compare condition is met. 10.4.6 mcu wait mode operation the wait instruction puts the mcu in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until completion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion cloc k source in wait is dependent on the definition of altclk for this mcu. consult the module introduct ion for information on altclk specific to this mcu. a conversion complete event sets the coco and genera tes an adc interrupt to wake the mcu from wait mode if the adc interrupt is enabled (aien = 1). 10.4.7 mcu stop3 mode operation the stop instruction is used to put the mcu in a low power-consumption standby mode during which most or all clock sources on the mcu are disabled. 10.4.7.1 stop3 mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion cl ock, executing a stop instruction aborts the current conversion and places the adc in its idle state. the contents of adcrh and adcrl are unaffected by stop3 mode.after exit ing from stop3 mode, a so ftware or hardware tr igger is required to resume conversions.
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 157 10.4.7.2 stop3 mode with adack enabled if adack is selected as the conversion clock, the adc conti nues operation during stop3 mode. for guaranteed adc operation, the mcu?s voltage regulator must remain active during stop3 mode. consult the module introduction for configur ation information for this mcu. if a conversion is in progress when the mcu enters stop3 mode, it cont inues until completion. conversions can be initiated while the mcu is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. a conversion complete event sets the coco and gene rates an adc interrupt to wake the mcu from stop3 mode if the adc interrupt is enabled (aien = 1). note it is possible for the adc module to wake the system from low power stop and cause the mcu to begin consum ing run-level currents without generating a system level interrupt. to prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in section 10.4.4.2, ?completing conversions ) is cleared when entering stop3 and continuing adc conversions. 10.4.8 mcu stop1 and stop2 mode operation the adc module is automatically disabled when the mcu enters either stop1 or stop2 mode. all module registers contain their reset valu es following exit from stop1 or stop2. therefore the module must be re-enabled and re-configured foll owing exit from stop1 or stop2. 10.5 initialization information this section gives an example which provides some basic direction on how a us er would initialize and configure the adc module. the user has the flexibility of choosing between configuring the module for 8-bit or 10-bit resolution, single or continuous conve rsion, and a polled or interrupt approach, among many other options. refer to table 10-6 , table 10-7, and table 10-8 for information used in this example. note hexadecimal values designated by a pr eceding 0x, binary values designated by a preceding %, and decimal va lues have no preceding character. 10.5.1 adc module in itialization example 10.5.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. update the configuration register (adccfg) to select the input clock source and the divide ratio used to generate the internal cloc k, adck. this register is also used for sele cting sample time and low-power configuration.
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 158 freescale semiconductor 2. update status and control regi ster 2 (adcsc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. update status and control regist er 1 (adcsc1) to select whethe r conversions will be continuous or completed only once, and to en able or disable conversion comple te interrupts. the input channel on which conversions will be performed is also selected here. 10.5.1.2 pseudo ? code example in this example, the adc module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, wher e the internal ad ck clock will be derived from the bus clock divided by 1. adccfg = 0x98 (%10011000) bit 7 adlpc 1 configures for low pow er (lowers maximum clock speed) bit 6:5 adiv 00 sets the adck to the input clock 1 bit 4 adlsmp 1 configures for long sample time bit 3:2 mode 10 sets mode at 10-bit conversions bit 1:0 adiclk 00 selects bus clock as input clock source adcsc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress bit 6 adtrg 0 software trigger selected bit 5 acfe 0 compare function disabled bit 4 acfgt 0 not used in this example bit 3:2 00 unimplemented or reserved, always reads zero bit 1:0 00 reserved for freescale?s internal use; always write zero adcsc1 = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes bit 6 aien 1 conversion complete interrupt enabled bit 5 adco 0 one conversion only (continuous conversions disabled) bit 4:0 adch 00001 input channel 1 se lected as adc input channel adcrh/l = 0xxx holds results of conversion. read high byte (adcrh ) before low byte (adcrl) so that conversion data cannot be overwritten with data from the next conversion. adccvh/l = 0xxx holds compare value when compare function enabled apctl1=0x02 ad1 pin i/o control disabled. all other ad pins remain general purpose i/o pins apctl2=0x00 all other ad pins remain general purpose i/o pins
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 159 figure 10-14. initialization flowchart for example 10.6 application information this section contains information for using the adc module in applic ations. the adc has been designed to be integrated into a microcontroller for use in embedded cont rol applications requiring an a/d converter. 10.6.1 external pins and routing the following sections discuss the external pins associated with th e adc module and how they should be used for best results. 10.6.1.1 analog supply pins the adc module has analog power and ground supplies (v ddad and v ssad ) which are available as separate pins on some devi ces. on other devices, v ssad is shared on the same pin as the mcu digital v ss , and on others, both v ssad and v ddad are shared with the mcu digital supply pins. in these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolat ion between the supplies is maintained. when available on a separate pin, both v ddad and v ssad must be connected to th e same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. yes no reset initialize adc adccfg = $98 adcsc1 = $41 adcsc2 = $00 check coco=1? read adcrh then adcrl to clear coco bit continue
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 160 freescale semiconductor in cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the v ssad pin. this should be the only ground connection between these supplies if possible. the v ssad pin makes a good single point ground location. 10.6.1.2 analog reference pins in addition to the analog supplies, the adc module ha s connections for two reference voltage inputs. the high reference is v refh , which may be shared on the same pin as v ddad on some devices. the low reference is v refl , which may be shared on the same pin as v ssad on some devices. when available on a separate pin, v refh may be connected to the same potential as v ddad , or may be driven by an external source th at is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). when available on a separate pin, v refl must be connected to the same voltage potential as v ssad . both v refh and v refl must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current dema nd is a 0.1 f capacitor with good high fre quency characteristics. this capacitor is connected between v refh and v refl and must be placed as ne ar as possible to the packag e pins. resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. inductance in this path must be minimum (parasitic only). 10.6.1.3 analog input pins the external analog inputs ar e typically shared with di gital i/o pins on mcu devi ces. the pin i/o control is disabled by setting the appropriate control bit in one of the pin cont rol registers. conversions can be performed on inputs without the associated pin control register bit set. it is recommended that the pin control register bit always be set when using a pin as an analog i nput. this avoids problems with contention because the output buffer will be in its high impedan ce state and the pullup is disabled. also, the input buffer draws dc current when its input is not at either v dd or v ss . setting the pin contro l register bits for all pins used as analog inputs should be done to achieve lowest operating current. empirical data shows that capacito rs on the analog inputs improve perfor mance in the presence of noise or when the source impeda nce is high. use of 0.01 f capacitors with good high-frequency characteristics is sufficient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to $3ff (full scale 10-bit representation) or $ff (full scale 8-bit re presentation). if the input is equal to or less than v refl , the converter circuit converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. there will be a brief current associated with v refl when the sampling capacitor is charging. the input is sampled for 3.5 cycles of the adck source when adlsmp is low, or 23.5 cycles when adlsmp is high. for minimal loss of accuracy due to curr ent injection, pins adjacent to th e analog input pins should not be transitioning during conversions.
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 161 10.6.2 sources of error several sources of error exist for a/d conversions. these are discussed in the following sections. 10.6.2.1 sampling error for proper conversions, the input mu st be sampled long eno ugh to achieve the prope r accuracy. given the maximum input resistance of approximately 7k and input capacitance of a pproximately 5.5 pf, sampling to within 1/4 lsb (at 10-bit resolution) can be achieved with in the minimum sample window (3.5 cycles @ 8 mhz maximum adck frequency) provided the re sistance of the external analog source (r as ) is kept below 5 k . higher source resistances or higher-accuracy sampli ng is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 10.6.2.2 pin leakage error leakage on the i/o pins can cause conversion erro r if the external analog source resistance (r as ) is high. if this error cannot be tolera ted by the application, keep r as lower than v ddad /(2 n *i leak ) for less than 1/4 lsb leakage error (n = 8 in 8-bi t mode or 10 in 10-bit mode). 10.6.2.3 noise-induced errors system noise which occurs during the sample or conversion process can affe ct the accuracy of the conversion. the adc accuracy numbers are guaranteed as specified only if the following conditions are met: ? there is a 0.1 f low-esr capacitor from v refh to v refl . ? there is a 0.1 f low-esr capacitor from v ddad to v ssad . ? if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v ddad to v ssad . ?v ssad (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. ? operate the mcu in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the adc conversion. ? for software triggered convers ions, immediately follow the writ e to the adcsc1 with a wait instruction or stop instruction. ? for stop3 mode operation, select adack as th e clock source. operation in stop3 reduces v dd noise but increases effective conve rsion time due to stop recovery. ? there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where ex ternal system activity causes radiat ed or conducted noi se emissions or excessive v dd noise is coupled into the adc. in these situ ations, or when the mcu cannot be placed in wait or stop3 or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: ? place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssad (this will improve noise issues but will affect sample ra te based on the external analog source resistance).
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 162 freescale semiconductor ? average the result by converti ng the analog input many times in succession and dividing the sum of the results. four samples are requi red to eliminate the effect of a 1 lsb , one-time error. ? reduce the effect of synchronous noise by ope rating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 10.6.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). each step ideally has the same height (1 code) and width. the width is defined as the de lta between the transition points to one code and the next. the ideal code width fo r an n bit converter (in this case n can be 8 or 10), defined as 1 lsb , is: 1 lsb = (v refh - v refl ) / 2 n eqn. 10-2 there is an inherent quantization e rror due to the digitizati on of the result. for 8-bit or 10-bit conversions the code will transition when the voltage is at th e midpoint between the points where the straight line transfer function is exactly repres ented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code width of the first ($000) conversion is only 1/2 lsb and the code width of the last ($ff or $3ff) is 1.5 lsb . 10.6.2.5 linearity errors the adc may also exhibit non-linearity of several forms. every effort has been made to reduce these errors but the system should be aware of them beca use they affect overall accuracy. these errors are: ? zero-scale error (e zs ) (sometimes called offset ) ? this error is defined as the difference between the actual code width of the first c onversion and the ideal code width (1/2 lsb ). note, if the first conversion is $001, then the difference betwee n the actual $001 code width and its ideal (1 lsb ) is used. ? full-scale error (e fs ) ? this error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5 lsb ). note, if the last conversion is $3fe, then the difference between the actual $3fe code width and its ideal (1 lsb ) is used. ? differential non-linearity (dnl) ? this error is de fined as the worst-case difference between the actual code width and the ideal code width for all conversions. ? integral non-linearity (inl) ? this error is defined as the highest-val ue the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. ? total unadjusted error (tue) ? this error is defi ned as the difference between the actual transfer function and the ideal straight-line transfer f unction, and therefore includes all forms of error. 10.6.2.6 code jitter, non-monotonicity and missing codes analog-to-digital converters are susceptible to thr ee special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain poi nts, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is infinitesi mally smaller than the transition voltage, the
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 163 converter yields the lower code (a nd vice-versa). however, even very small amounts of system noise can cause the converter to be indete rminate (between two codes) for a range of input voltages around the transition voltage. this ra nge is normally around 1/2 lsb and will increase with noise. this error may be reduced by repeatedly samp ling the input and averaging the result . additionally the techniques discussed in section 10.6.2.3 will reduce this error. non-monotonicity is defined as when, except for code jitter, the convert er converts to a lower code for a higher input voltage. missing codes are those values which are never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and to have no missing codes.
analog-to-digital converter (s08adc10v1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 164 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 165 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introduction the inter-integrated circuit (iic) provides a method of commu nication between a numb er of devices. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of de vices that can be conn ected are limited by a maximum bus capacitance of 400 pf. note the sda and scl should not be driven above v dd . these pins are pseudo-open-drain containing a protection diode to v dd . 11.1.1 module configuration the iic module pins, sda and scl, can be reposit ioned under software control using iicps in sopt1, as as shown in table 11-1 . this bit selects which general-purpose i/o ports are associated with iic operation. figure 11-1 shows the mc9s08el32 series and mc9s08sl16 series block diagram with the iic module highlighted. table 11-1. iic position options sopt1[iicps] port pin for sda port pin for scl 0 (default pta2 pta3 1p t b 6p t b 7
chapter 11 inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 166 freescale semiconductor figure 11-1. mc9s08el32 block diagra m highlighting iic block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 167 11.1.2 features the iic includes these distinctive features: ? compatible with iic bus standard ? multi-master operation ? software programmable for one of 64 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection ? general call recognition ? 10-bit address extension 11.1.3 modes of operation a brief description of the iic in th e various mcu modes is given here. ? run mode ? this is the basic mode of operation. to conserve power in th is mode, disable the module. ? wait mode ? the module continues to operate while th e mcu is in wait mode and can provide a wake-up interrupt. ? stop mode ? the iic is inactive in stop3 mode fo r reduced power consumption. the stop instruction does not affect iic register st ates. stop2 resets the register contents.
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 168 freescale semiconductor 11.1.4 block diagram figure 11-2 is a block diagram of the iic. figure 11-2. iic functional block diagram 11.2 external signal description this section describes each user-accessible pin signal. 11.2.1 scl ? serial clock line the bidirectional scl is the serial clock line of the iic system. 11.2.2 sda ? serial data line the bidirectional sda is the serial data line of the iic system. 11.3 register definition this section consists of the iic register descriptions in address order. input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 169 refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 iic address register (iica) 11.3.2 iic frequency divider register (iicf) 76543210 r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w r e s e t00000000 = unimplemented or reserved figure 11-3. iic address register (iica) table 11-2. iica field descriptions field description 7?1 ad[7:1] slave address. the ad[7:1] field contains the slave address to be used by the iic module. this field is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 76543210 r mult icr w r e s e t00000000 figure 11-4. iic frequency divider register (iicf)
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 170 freescale semiconductor for example, if the bus speed is 8 m hz, the table below shows the possibl e hold time values with different icr and mult selections to achie ve an iic baud rate of 100kbps. table 11-3. iicf field descriptions field description 7?6 mult iic multiplier factor . the mult bits define the multiplier factor, mu l. this factor, along with the scl divider, generates the iic baud rate. the multiplier factor mu l as defined by the mult bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 reserved 5?0 icr iic clock rate . the icr bits are used to prescale the bus clock for bit rate selection. these bits and the mult bits determine the iic baud rate, the sda hold time, the scl start hold time, and the scl stop hold time. ta b l e 1 1 - 5 provides the scl divider and hold values for corresponding values of the icr. the scl divider multiplied by multiplier factor mul generates iic baud rate. eqn. 11-1 sda hold time is the delay from the falling edge of scl (iic clock) to the changing of sda (iic data). sda hold time = bus period (s) mul sda hold value eqn. 11-2 scl start hold time is the delay from the falling edge of sda (iic data) while scl is high (start condition) to the falling edge of scl (iic clock). scl start hold time = bus period (s) mul scl start hold value eqn. 11-3 scl stop hold time is the delay from the rising edge of scl (iic clock) to the rising edge of sda sda (iic data) while scl is high (stop condition). scl stop hold time = bus period (s) mul scl stop hold value eqn. 11-4 table 11-4. hold time values for 8 mhz bus speed mult icr hold times ( s) sda scl start scl stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0b 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 iic baud rate bus speed (hz) mul scldivider -------------------------------------------- - =
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 171 table 11-5. iic divider and hold values icr (hex) scl divider sda hold value scl hold (start) value sda hold (stop) value icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0a 36 9 14 19 2a 448 65 222 225 0b 40 9 16 21 2b 512 65 254 257 0c 44 11 18 23 2c 576 97 286 289 0d 48 11 20 25 2d 640 97 318 321 0e 56 13 24 29 2e 768 129 382 385 0f 68 13 30 35 2f 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1a 112 17 54 57 3a 1792 257 894 897 1b 128 17 62 65 3b 2048 257 1022 1025 1c 144 25 70 73 3c 2304 385 1150 1153 1d 160 25 78 81 3d 2560 385 1278 1281 1e 192 33 94 97 3e 3072 513 1534 1537 1f 240 33 118 121 3f 3840 513 1918 1921
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 172 freescale semiconductor 11.3.3 iic control register (iicc1) 11.3.4 iic status register (iics) 76543210 r iicen iicie mst tx txak 000 w rsta r e s e t00000000 = unimplemented or reserved figure 11-5. iic control register (iicc1) table 11-6. iicc1 field descriptions field description 7 iicen iic enable. the iicen bit determines whether the iic module is enabled. 0 iic is not enabled 1 iic is enabled 6 iicie iic interrupt enable. the iicie bit determines whether an iic interrupt is requested. 0 iic interrupt request not enabled 1 iic interrupt request enabled 5 mst master mode select. the mst bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0slave mode 1 master mode 4 tx transmit mode select. the tx bit selects the direction of master and slave transfers. in master mode, this bit should be set according to the type of transfer required. therefore, for address cycles, this bit is always high. when addressed as a slave, this bit should be set by software according to the srw bit in the status register. 0 receive 1 transmit 3 txak transmit acknowledge enable. this bit specifies the value driven onto the sda during data acknowledge cycles for master and slave receivers. 0 an acknowledge signal is sent out to the bus after receiving one data byte 1 no acknowledge signal response is sent 2 rsta repeat start. writing a 1 to this bit generates a repeated start condition provided it is the current master. this bit is always read as cleared. attempting a repeat at the wrong time results in loss of arbitration. 76543210 rtcf iaas busy arbl 0srw iicif rxak w r e s e t10000000 = unimplemented or reserved figure 11-6. iic status register (iics)
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 173 11.3.5 iic data i/o register (iicd) table 11-7. iics field descriptions field description 7 tcf transfer complete flag. this bit is set on the completion of a byte transfer. this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iicd register in receive mode or writing to the iicd in transmit mode. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave. the iaas bit is set when the calling address matches the programmed slave address or when the gcaen bit is set and a general call is received. writing the iicc register clears this bit. 0 not addressed 1 addressed as a slave 5 busy bus busy. the busy bit indicates the status of the bus regardl ess of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 0 bus is idle 1bus is busy 4 arbl arbitration lost. this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software by writing a 1 to it. 0 standard bus operation 1 loss of arbitration 2 srw slave read/write. when addressed as a slave, the srw bit indica tes the value of the r/w command bit of the calling address sent to the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 iicif iic interrupt flag. the iicif bit is set when an interrupt is pendi ng. this bit must be cleared by software, by writing a 1 to it in the interrupt routine. o ne of the following events can set the iicif bit: ? one byte transfer completes ? match of slave address to calling address ? arbitration lost 0 no interrupt pending 1 interrupt pending 0 rxak receive acknowledge . when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 0 acknowledge received 1 no acknowledge received 76543210 r data w r e s e t00000000 figure 11-7. iic data i/o register (iicd)
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 174 freescale semiconductor note when transitioning out of master r eceive mode, the iic mode should be switched before reading the iicd register to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are avai lable after an addres s match has occurred. the tx bit in iicc must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is c onfigured for master transmit but a master receive is desired, reading the iicd does not initiate the receive. reading the iicd returns the last byte received while the iic is configured in master receive or slave receive modes. the iicd does not reflect every byte transmitted on the iic bus, nor can software verify that a byte has been written to the iicd correctly by reading it back. in master transmit mode, th e first byte of data written to iicd foll owing assertion of ms t is used for the address transfer and should comprise of the calling addr ess (in bit 7 to bit 1) conc atenated with the required r/w bit (in position bit 0). 11.3.6 iic control register 2 (iicc2) table 11-8. iicd field descriptions field description 7?0 data data ? in master transmit mode, when data is written to t he iicd, a data transfer is init iated. the most significant bit is sent first. in master receive mode, reading this register initiates receiving of the ne xt byte of data. 76543210 r gcaen adext 000 ad10 ad9 ad8 w r e s e t00000000 = unimplemented or reserved figure 11-8. iic control register (iicc2) table 11-9. iicc2 field descriptions field description 7 gcaen general call address enable. the gcaen bit enables or disables general call address. 0 general call address is disabled 1 general call address is enabled 6 adext address extension. the adext bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2?0 ad[10:8] slave address. the ad[10:8] field contains the upper three bits of the slave address in the 10-bit address scheme. this field is only valid when the adext bit is set.
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 175 11.4 functional description this section provides a complete func tional description of the iic module. 11.4.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for da ta transfer. all devices connected to it must have open drain or open collec tor outputs. a logic and function is exercised on both lines with external pull-up resistors. the va lue of these resistors is system dependent. normally, a standard communication is composed of four parts: ? start signal ? slave address transmission ? data transfer ? stop signal the stop signal should not be confus ed with the cpu stop instruction. the iic bus system communication is described briefly in the follow ing sections and illustrated in figure 11-9 . figure 11-9. iic bus transmission signals 11.4.1.1 start signal when the bus is free, no master de vice is engaging the bus (scl and sda lines are at logical high), a master may initiate communication by se nding a start signal. as shown in figure 11-9, a start signal is defined as a high-to-low transition of sda while scl is high. this si gnal denotes the beginning of a new data transfer (each data transfer ma y contain several bytes of data) and br ings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 12 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 176 freescale semiconductor 11.4.1.2 slave address transmission the first byte of data transferred im mediately after the start signal is th e slave address transmitted by the master. this is a seven-bit ca lling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling addr ess that matches the one transmitt ed by the master responds by sending back an acknowledge bit. this is done by pul ling the sda low at the ninth clock (see figure 11-9 ). no two slaves in the system may have the same a ddress. if the iic module is the master, it must not transmit an address equal to its own slave address. the iic cannot be ma ster and slave at the same time. however, if arbitration is lost during an address cycle, the iic reverts to slave mode and operates correctly even if it is being a ddressed by another master. 11.4.1.3 data transfer before successful slave addressing is achieved, the da ta transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 11-9 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at th e ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowledge the master in the ninth bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsu ccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is abor ted and the master does one of two things: ? relinquishes the bus by generating a stop signal. ? commences a new calling by gene rating a repeated start signal. 11.4.1.4 stop signal the master can terminate the comm unication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a ca lling command without gene rating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-h igh transition of sda while scl at logical 1 (see figure 11-9 ). the master can generate a stop even if the slave ha s generated an acknowledge at which point the slave must release the bus.
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 177 11.4.1.5 repeated start signal as shown in figure 11-9 , a repeated start signal is a start signa l generated without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (tra nsmit/receive mode) wit hout releasing the bus. 11.4.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a cl ock synchronization proce dure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the c ontending masters is determin ed by a data arbitration procedure, a bus master lose s arbitration if it transm its logic 1 while another ma ster transmits logic 0. the losing masters immediately switch ove r to slave receive mode and stop driving sda output. in this case, the transition from master to slave mode does not ge nerate a stop condition. meanwh ile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. th e devices start counting their low pe riod and after a device?s clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 11-10 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again. figure 11-10. iic clock synchronization scl1 scl2 scl internal counter reset delay start counting high period
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 178 freescale semiconductor 11.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byt e transfer (9 bits). in such a ca se, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 11.4.1.9 clock stretching the clock synchronization mechanism ca n be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive sc l low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 11.4.2 10-bit address for 10-bit addressing, 0x11110 is used fo r the first 5 bits of the first addr ess byte. various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 master-transmitter addresses a slave-receiver the transfer direction is not changed (see table 11-10). when a 10-bit address follows a start condition, each slave compares the first seven bits of the fi rst byte of the slave address (11110xx) with its own address and tests whet her the eighth bit (r/w direction bit) is 0. more than one device can find a match and generate an acknowledge (a1). then, each slave that finds a matc h compares the eight bits of the second byte of the slave a ddress with its own addre ss. only one slave finds a match and generates an acknowledge (a2). the matchi ng slave remains addressed by the mast er until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.2.2 master-receiver addr esses a slave-transmitter the transfer direction is changed after the second r/w bit (see table 11-11 ). up to and including acknowledge bit a2, the pro cedure is the same as th at described for a master-transmitter addressing a slave-receiver. after the repeated start condition (sr), a matching slav e remembers that it was addressed before. this slave then checks whether the first seven bits of the first byte of the slave address following sr are the same as they were after the start condition (s) a nd tests whether the eighth (r/w ) bit is 1. if there is a match, the slave considers that it has been addresse d as a transmitter and generates acknowledge a3. the slave-transmitter remains addres sed until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 data a ... data a/a p 11110 + ad10 + ad9 0 ad[8:1] table 11-10. master-transmitter addresses slave-receiver with a 10-bit address
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 179 after a repeated start condition (sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (r/w ) bit. however, none of them are addressed because r/w = 1 (for 10-bit devices) or the 11110xx slave address (for 7-bit devices) does not match. after the master-receiver has sent the first byte of th e 10-bit address, the slav e-transmitter sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.3 general call address general calls can be requested in 7- bit address or 10-bit addr ess. if the gcaen bit is set, the iic matches the general call address as well as its own slave addres s. when the iic responds to a general call, it acts as a slave-receiver and the iaas bit is set after the address cycl e. software must read the iicd register after the first byte transfer to determine whether the address matche s is its own slave addr ess or a general call. if the value is 00, the match is a ge neral call. if the gcaen bit is clear , the iic ignores any data supplied from a general call address by not issuing an acknowledgement. 11.5 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 11.6 interrupts the iic generates a single interrupt. an interrupt from the iic is gene rated when any of the events in table 11-12 occur, provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by software by writing a 1 to it in the interrupt routine. you can determine the interrupt type by reading the status register. 11.6.1 byte transfer interrupt the tcf (transfer complete flag) bit is set at the falling edge of the ni nth clock to indica te the completion of byte transfer. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 sr slave address 1st 7 bits r/w a3 data a ... data a p 11110 + ad10 + ad9 0 ad[8:1] 11110 + ad10 + ad9 1 table 11-11. master-receiver addresses a slave-transmitter with a 10-bit address table 11-12. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 180 freescale semiconductor 11.6.2 address detect interrupt when the calling address matches the programmed slav e address (iic address register) or when the gcaen bit is set and a general call is received, the ia as bit in the status register is set. the cpu is interrupted, provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. 11.6.3 arbitration lost interrupt the iic is a true mul ti-master bus that allows more than one mast er to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of th e contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt wh en it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in th e following circumstances: ? sda sampled as a low when the master drives a high during an address or data transmit cycle. ? sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. this bit must be cleared by software writing a 1 to it.
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 181 11.7 initialization/application information figure 11-11. iic module quick start module initialization (slave) 1. write: iicc2 ? to enable or disable general call ? to select 10-bit or 7-bit addressing mode 2. write: iica ? to set the slave address 3. write: iicc1 ? to enable iic and interrupts 4. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 5. initialize ram variables used to achieve the routine shown in figure 11-12 module initialization (master) 1. write: iicf ? to set the iic baud rate (examp le provided in this chapter) 2. write: iicc1 ? to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 11-12 5. write: iicc1 ? to enable tx 0 iicf iica baud rate = busclk / (2 x mult x (scl divider)) tx txak rsta 0 0 iicc1 iicen iicie mst module configuration arbl 0 srw iicif rxak iics tcf iaas busy module status flags register model ad[7:1] when addressed as a slave (in slave mode), the module responds to this address mult icr iicd data data register; write to transmit iic data read to read iic data 0 ad10 ad9 ad8 iicc2 gcaen adext address configuration 0 0
inter-integrated circuit (s08iicv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 182 freescale semiconductor figure 11-12. typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to iicd switch to rx mode dummy read from iicd generate stop signal read data from iicd and store set txack =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear arbl iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to iicd set rx mode dummy read from iicd ack from receiver ? tx next byte read data from iicd and store switch to rx mode dummy read from iicd rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iicif address transfer data transfer (mst = 0) (mst = 0) see note 1 notes: 1. if general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). if the received address was a general call address, then the general call must be handled by user software. 2. when 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended addre ss. user software must ensure that for this interrupt, the content s of iicd are ignored and not treated as a valid data transfer see note 2
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 185 chapter 12 slave lin interface controller (s08slicv1) 12.1 introduction the slave lin interface controller (slic) is designed to provide slave node connectivity on a local interconnect network (lin) s ub-bus. lin is an open-standa rd serial protocol deve loped for the automotive industry to connect sensors, motors, and actuators.
chapter 12 slave lin interface controller (s08slicv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 186 freescale semiconductor figure 12-1. mc9s08el32 block diagra m highlighting slic block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 187 12.1.1 features the slic includes these distinctive features: ? full lin message buffering of identifier and 8 data bytes ? automatic bit rate and lin message frame synchronization: ? no prior programming of bit rate re quired, 1?20 kbps lin bus speed operation ? all lin messages will be received (no message loss due to synchronization process) ? input clock tolerance as high as 50%, allowing internal osci llator to remain untrimmed ? incoming break symbols always allowed to be 10 or more bit times without message loss ? supports automatic software trimming of intern al oscillator using lin synchronization data ? automatic processing a nd verification of lin synch break and synch byte ? automatic checksum calculation and verification with error reporting ? maximum of two interrupts per standa rd lin message frame with no errors ? full lin error checking and reporting ? high-speed lin capability up to 83.33 kbps to 120.00 kbps 1 ? configurable digital receive filter ? streamlined interrupt servicing throug h use of a state vector register ? switchable uart-like byte transf er mode for processing bytes one at a time without lin message framing constraints ? enhanced checksum (includes id) generation and verification 1. maximum bit rate of slic module dependent upon frequency of slic input clock.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 188 freescale semiconductor 12.1.2 modes of operation figure 12-2 shows the modes in which the slic will operate. figure 12-2. slic operating modes 12.1.2.1 power off this mode is entered from the reset mode whenever the slic module supply voltage v dd drops below its minimum specified value for the slic module to guara ntee operation. the slic m odule will be placed in the reset mode by a system low-voltage reset (lvr) before being powered down. in this mode, the pin input and output specificat ions are not guaranteed. 12.1.2.2 reset this mode is entered from the power off m ode whenever the slic module supply voltage v dd rises above its minimum specified value (v dd(min) ) and some mcu reset source is asserted. to prevent the slic from entering an unknown state, the internal mcu reset is asserted while powering up the slic module. slic reset mode is also entered fr om any other mode as soon as one of the mcu's possible reset sources (e.g., lvr, por, cop, rst pin, etc.) is asserted. slic reset mode may also be entered by the user software by asserting the initreq bi t. initack indicates whether the sl ic module is in the reset mode as a result of writing initreq in slcc1. wh ile in the reset state the sl ic module clocks are stopped. clearing the initreq allows the slic to proceed and enter slic run m ode (if slce is set). the module v dd > v dd (min) and any slic reset slic disabled slic run slic init requested slic stop slic wait mcu reset source asserted power off no mcu reset source asserted slce set in slcc2 register network activity or other mcu wakeup (wait instruction and slcwcm = 0) stop instruction (wait instruction and slcwcm = 1) slcie=1 and network activity or other mcu wakeup slce cleared in slcc2 register (initack = 1) (from any mode) initreq set to 1 in slcc1 register (from any mode) any mcu reset source asserted v dd <= v dd (min) initreq = 0; (initack = 0)
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 189 will clear initack after the module ha s left reset mode and the slic will seek the next lin header. it is the responsibility of the user to ve rify that this operation is compat ible with the a pplication before implementing this feature. in this mode, the internal slic modul e voltage references are operative, v dd is supplied to the internal circuits, which are held in their reset state and the internal slic module system clock is running. registers will assume their reset condition. outputs are held in their programmed reset state, inputs and network activity are ignored. 12.1.2.3 slic disabled this mode is entered from the reset mode after all mcu reset sources are no l onger asserted or initreq is cleared by the user and the slic module clears initack. it is entered from the run mode whenever slce in slcc2 is cleared. in this mode the slic clock is stopped to conserve power and allow the slic module to be configured for proper operation on the lin bus. 12.1.2.4 slic run this mode is entered from the slic disabled mode wh en slce in slcc2 is set. it is entered from the slic wait mode whenever activity is sensed on the lin bus or some other mcu source wakes the cpu out of wait mode. it is entered from the slic stop m ode whenever network activity is sensed or some other mcu source wakes the cpu out of stop mode. messages will not be received properly until the clocks have stabilized and the cpu is also in the run mode. 12.1.2.5 slic wait this power conserving mode is automatically entered from the run mode when ever the cpu executes a wait instruction and slcwcm in sl cc1 is previously cleared. in this mode, the slic module internal clocks continue to run. any activity on the lin netw ork will cause the slic module to exit slic wait mode and return to slic run. no activity for an a time on the lin bus will also cause the no bus activity interrupt source to occur. this will also cause an exit from slic wait mode. 12.1.2.6 wakeup from slic wait with cpu in wait if the cpu executes the wait instru ction and the slic modul e enters the wait mode (slcwcm = 0), the clocks to the slic module as well as the clocks in the mcu continue to run. therefore, the message that wakes up the slic module from wait and the cpu from wait mode will also be received correctly by the slic module. this is because all of the required clocks continue to run in the slic module in wait mode. 12.1.2.7 slic stop this power conserving mode is automatically entered from the run mode when ever the cpu executes a stop instruction, or if the cpu executes a wait in struction and slcwcm in slcc1 is previously set. in this mode, the slic internal cl ocks are stopped. if slic interrupts are enabled (slcie = 1) prior to
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 190 freescale semiconductor entering slic stop mode, any activit y on the network will cause the slic module to exit slic stop mode and generate an unmaskable interrupt of the cpu. this wakeup interrupt state is reflected in the slcsv, encoded as the highest priority interrupt. this inte rrupt can be cleared by the cpu with a read of the slcsv and clearing of the slcf interrupt flag. depending upon which low-power mode instruction the cpu executes to cause the slic module to enter sl ic stop, the message which wakes up the slic module (and the cpu) may or may not be received. there are two different possibilities: 1. wakeup from slic stop with cpu in stop when the cpu executes the stop in struction, all clocks in the mcu, including clocks to the slic module, are turned off. therefore, the message which wakes up the slic module and the cpu from stop mode will not be received. this is due primarily to the amount of time required for the mcu's oscillator to stabilize before the clocks can be applied internally to the other mcu modules, including the slic module. 2. wakeup from slic stop with cpu in wait. if the cpu executes the wait instruction and the slic module enters the stop mode (slcwcm = 1), the clocks to th e slic module are turned off, but the clocks in the mcu continue to run. th erefore, the message which wakes up the slic module from stop and the cpu from wait mode will be received correctly by the slic module. this is because very little time is required for the cpu to turn th e clocks to the slic module back on after the wakeup interrupt occurs. note while the slic module will correctly receive a message which arrives when the slic module is in stop or wait mode and the mcu is in wait mode, if the user enters this mode while a message is being received, the data in the message will become corrupt ed. this is due to the steps required for the slic module to resume opera tion upon exiting stop or wait mode, and its subsequent resynchr onization with the lin bus. 12.1.2.8 normal and emul ation mode operation the slic module operates in the same manner in all normal and emulation modes. all slic module registers can be read and written except those that are reserved, unimplemented, or write once. the user must be careful not to unintentiona lly change reserved bits to avoid unexpected slic module behavior. 12.1.2.9 special mode operation some aspects of slic module operati on can be modified in special test mode. this mode is reserved for internal use only. 12.1.2.10 low-power options the slic module can save power in disabled, wait, and stop modes.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 191 12.1.3 block diagram figure 12-3. slic module block diagram 12.2 external signal description 12.2.1 slctx ? slic transmit pin the slctx pin serves as the serial output of the slic module. 12.2.2 slcrx ? slic receive pin the slcrx pin serves as the serial input of the slic m odule. this input feeds into the digital receive filter block which filters out noise glitches from the incoming data stream. 12.3 register definition 12.3.1 slic control register 1 (slcc1) slic control register 1 (slcc1) contains bits used to control various basic features of the slic module, including features used for in itialization and at runtime. status registers control registers bus clock message buffer ? 9 bytes slcid slcd7, slcd6, slcd5, slcd4 shadow register 1 byte lin protocol state machine (psm) digital rx filter slcrx slctx slcsv slcsv and slcf digital rx filter prescaler (rxfp) slic clock slcd3, slcd2, slcd1, slcd0 register control
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 192 freescale semiconductor 76543210 r0 0 initreq bedd waketx txabrt imsg slcie w r e s e t00100000 = unimplemented or reserved figure 12-4. slic control register 1 (slcc1) table 12-1. slcc1 field descriptions field description 5 initreq initialization request ? requesting initialization mode by setting this bit will place the slic module into its initialized state immediately. as a result of setting in itreq, initack will be set in slcs. initack = 1 causes all slic register bits (except slcwcm: write once) to be held in their reset states and become not writable until initack has been cleared. if transmission or reception of data is in progress, the transaction will be terminated immediately upon entry into initialization mode (signified by initack being set to 1). to return to normal slic operation after the slic has been initialized (the initack is high), the initreq must be cleared by software. 0 normal operation 1 request for slic to be put into reset state immediately 4 bedd bedd bit error detection disable ? this bit allows the user to disable bit error detection circuitry. bit error detection monitors the received bits to determine if th ey match the state of the corresponding transmitted bits. when bit error detection is enabled and a mismatch between transmitted bit and received bit is detected, a bit error is reported to the user through the slcsv register and a slic interrupt is generated (if slic interrupts are enabled). the user must ensure that all physical de lays which affect the timing of received bits are not significant enough to cause the bit error detection circ uitry to incorrectly detect bit errors at higher lin bus speeds. see section 12.6.15, ?bit error detection and physical layer delay ,? for details. note bit error detection is not reco mmended for use in btm mode, as bit errors are reporte d on bit boundaries, not byte boundaries. this can result in misaligned data. bit errors must not be disabl ed during normal lin operations, as it allows the slic module to operate outside of the lin specification. if you switch off bit error detection, there is no guaranteed way to detect bus collisions and automatically cease transmissions. therefor e pending slic transmissions may continue after a bit error should have been detected, potentially corrupting bus traffic. 0 bit error detection enabled 1 bit error detection disabled no bit errors will be detected or reported 3 waketx transmit wakeup symbol ? this bit allows the user to transmit a wakeup symbol on the lin bus. when set, this sends a wakeup symbol, as defined in the lin specification a single time, then resets to 0. this bit will read 1 while the wakeup symbol is being transmitted on the bu s. this bit will be automatically cleared when the wakeup symbol is complete. 0 normal operation 1 send wakeup symbol on lin bus
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 193 12.3.2 slic control register 2 (slcc2) slic control register 2 (slcc2) c ontains bits used to control various features of the slic module. 2 txabrt transmit abort message 0 normal operation 1 transmitter aborts current transmission at next byte boundary; txabrt resets to 0 after the transmission is successfully aborted txabrt also resets to 0 upon detection of a bit error. 1 imsg slic ignore message bit ? imsg cannot be cleared by a write of 0, but is cleared automat ically by the slic module after the next break/sync symbol pair is validated. after it is set, imsg will not keep data from being written to the receive data buffer, which means that the buffers cannot be assumed to contain known valid message data until the next receive buffer full interrupt. imsg must not be used in btm mode. the slic automatically clears the imsg bit when entering mcu stop mode or mcu wait mode with slcwcm bit set. 0 normal operation1slic interrupts (except "no bus acti vity") are suppressed until the next message header arrives 0 slcie slic interrupt enable 0 slic interrupt sources are disabled 1 slic interrupt sources are enabled 76543210 r0 rxfp slcwcm btm 0 slce w r e s e t01000000 = unimplemented or reserved figure 12-5. slic control register 2 (slcc2) table 12-1. slcc1 field descriptions (continued) field description
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 194 freescale semiconductor table 12-2. slcc2 field descriptions field description 6:4 rxfp receive filter prescaler ? these bits configure the effe ctive filter width for the digital receive filter circuit. the rxfp bits control the maximum number of slic clock counts required for the filt er to change state, which determines the total maximum filter delay. any pulse whic h is smaller than the maximu m filter delay value will be rejected by the filter and ignored as noise. for this reason, the user must choose the prescaler value appropriately to ensure that all valid message traffic is able to pass the filter for the desired bit rate. for more details about setting up the digital receive filter, please refer to section 12.6.18, ?digital receive filter .? the frequency of the slic clock must be between 2 mhz and 20 mhz, factoring in worst case possible numbers due to untrimmed process variations, as well as temperat ure and voltage variations in oscillator frequency. this will guarantee greater than 1.5% accuracy for all lin messa ges from 1?20 kbps. the faster this input clock is, the greater the resulting accuracy and the higher the possible bit rates at which the slic can send and receive. in lin systems, the bit rates will not exceed 20 kbps; howe ver, the slic module is capable of much higher speeds without any configuration changes, for cases such as high-speed downloads for reprogramming of flash memory or diagnostics in a test environment where radiat ed emissions requirements are not as stringent. in these situations, the user may choos e to run faster than the 20 kbps limit which is imposed by the lin specification for emc reasons. details of how to calc ulate maximum bit rates and operate the slic above 20 kbps are detailed in .? refer to section 12.6.6, ?slic module initialization procedure ,? for more information on when to set up this register. see table 12-3 . 3 slcwcm slic wait clock mode ? this write-once bit can only be written once out of mcu reset state and should be written before slic is first enabled. 0 slic clocks continue to run when the cpu is placed into wait mode so that the slic can receive messages and wakeup the cpu. 1 slic clocks stop when the cpu is placed into wait mode 2 btm 1 1 to guarantee timing, the user must ensure that the slic cloc k used allows the proper communications timing tolerances and therefore internal oscillator circuits mi ght not be appropriate for use with btm mode. uart byte transfer mode ? byte transmit mode bypasses the normal lin message framing and checksum monitoring and allows the user to send and receive single bytes in a method similar to a half-duplex uart. when enabled, this mode reads the bit time register (slcbt) va lue and assumes this is the value corresponding to the number of slic clock counts for one bit time to esta blish the desired uart bit rate. the user software must initialize this register prior to sending or receiving dat a, based on the input clock selection, prescaler stage choice, and desired bit rate. if this bit is cleared du ring a byte transmission, that byte transmission is halted immediately. btm treats any data length in slcdlc as one byte (dlc = 0x00) and disables the checksum circuitry so that chkmod has no effect. refer to section 12.6.16, ?byte transfer mode operation ,? for more detailed information about how to use this mode. btm sets up the slic modul e to send and receive one byte at a time, with 8-bit data, no parity, and one stop bit (8-n-1). this is t he most commonly used setup for uart communications and should work for most applications. this is fixed in the slic and is not configurable. 0 uart byte transfer mode disabled 1 uart byte transfer mode enabled 0 slce slic module enable ? controls the clock to the slic module 0 slic module disabled 1 slic module enabled
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 195 12.3.3 slic bit time regi sters (slcbth, slcbtl) note in this subsection, the slic bit time registers are collectivel y referred to as slcbt. in lin operating mode (btm = 0), the slcbt is upda ted by the slic upon recep tion of a li n break-sync combination and provides the number of slic clock counts that equal one lin bit time to the user software. this value can be us ed by the software to calculate the clock dr ift in the oscillator as an offset to a known count value (based on nominal oscillator frequency and lin bus speed). the user software can then trim the oscillator to comp ensate for clock drift. refer to section 12.6.17, ?oscillat or trimming with slic ,? for more information on this procedure. the user should only read th e bit time value from slcbth and slcbtl in the interrupt service routine code for reception of the identifier byte. reads at any other time during lin activity may not provi de reliable results. when in byte transfer mode (btm = 1), the slcbt must be written by the user to set the length of one bit at the desired bit rate in slic clock counts. the user software must initialize this number prior to sending or receiving data, based on the input clock sel ection, prescaler stage choice, and desired bit rate. this setting is similar to choosing an input capture or output compare value for a timer. a write to both registers is required to update the bit time value. note the slic bit time will not be upda ted until a write of the slcbtl has occurred. table 12-3. digital receive filter clock prescaler rxfp[2:0] digital rx filter clock prescaler (divide by) max filter delay (in s) filter input clock (slic clock in mhz) 2 4 6 8 10 12 14 16 18 20 000 1 8.00 4.00 2.67 2.00 1.60 1.33 1.14 1.00 0.89 0.80 001 2 16.00 8.00 5.33 4.00 3.20 2.67 2.29 2.00 1.78 1.60 010 3 24.00 12.00 8.00 6.00 4.80 4.00 3.43 3.00 2.67 2.40 011 4 32.00 16.00 10.67 8.00 6.40 5.33 4.57 4.00 3.56 3.20 100 5 40.00 20.00 13.33 10.00 8.00 6.67 5.71 5.00 4.44 4.00 101 6 48.00 24.00 16.00 12.00 9.60 8.00 6.86 6.00 5.33 4.80 110 7 56.00 28.00 18.67 14.00 11.20 9.33 8.00 7.00 6.22 5.60 111 8 64.00 32.00 21.33 16.00 12. 80 10.67 9.14 8.00 7.11 6.40
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 196 freescale semiconductor 12.3.4 slic status register (slcs) slic status register (slcs) c ontains bits used to monitor th e status of the slic module. 76543210 r0 bt14 bt13 bt12 bt11 bt10 bt9 bt8 w r e s e t00000000 = unimplemented or reserved 1 1 do not write to unimplemented bits as unexpected operation may occur. figure 12-6. slic bit time register high (slcbth) table 12-4. slcbth field descriptions field description 6:0 bt[14:8] bit time value ? bt displays the number of slic clocks that equals one bit time in lin mode (btm = 0). for details of the use of the slcbt r egisters in lin mode for trimming of the internal oscillator, refer to section 12.6.17, ?oscillator trimming with slic .? bt sets the number of slic clocks that equals one bit time in byte transfer mode (btm = 1). for details of the use of the slcbt registers in btm mode, refer to section 12.6.16, ?byte tr ansfer mode operation .? 76543210 r bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 w r e s e t00000000 = unimplemented or reserved 1 1 do not write to unimplemented bits as unexpected operation may occur. figure 12-7. slic bit time register low (slcbtl) table 12-5. slcbtl field descriptions field description 7:0 bt[7:0] bit time value ? bt displays the number of slic clocks that equals one bit time in lin mode (btm = 0). for details of the use of the slcbt r egisters in lin mode for trimming of the internal oscillator, refer to section 12.6.17, ?oscillator trimming with slic .? bt sets the number of slic clocks that equals one bit time in byte transfer mode (btm = 1). for details of the use of the slcbt registers in btm mode, refer to section 12.6.16, ?byte tr ansfer mode operation .?
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 197 12.3.5 slic state vect or register (slcsv) slic state vector register (slcsv) is provided to substantially decrease th e cpu overhead associated with servicing interrupts while under operation of a lin prot ocol. it provides an index offset that is directly related to the lin module?s current state, which can be used with a user supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the user to maintain a duplicate state machine in software. 76543210 r slcact 0 initack 0 0 0 0 slcf w r e s e t00100000 = unimplemented or reserved figure 12-8. slic status register (slcs) table 12-6. slcs field descriptions field description 7 slcact 1 1 slcact may not be clear during all idle times of the bus. for example, if imsg was used to ignore the data interrupts of an extended message frame, slcact will remain set until another lin message is received and either the rx message buffer full checksum ok (slcsv = 0x10) or the tx message buffer empty checksum transmitted (slcsv = 0x08) interrupt sources are asserted and cleared. when clear, slcact always indicates times when the slic module is not active, but it is possible for the slic module to be not active with slcact set. slcact has no meaning in btm mode. slic active (oscillator trim blocking semaphore) ? slcact is used to indicate if it is safe to trim the oscillator based upon current slic activity in lin mode. this bit indicates that the slic module might be currently receiving a message header, synchronization byte, id byte, or sending or receiving data bytes. this bit is read-only. this bit has no meaning in btm mode (btm =1). 0 slic module not active (safe to trim oscillator) slcact is cleared by the slic module only upon assertion of the rx message buffer full checksum ok (slcsv = 0x10) or the tx message buffer empty checksum transmitted (slcsv = 0x08) interrupt sources. 1 slic module activity (not safe to trim oscillator) slcact is automatically set to 1 if a falling edge is seen on the slcrx pin and has successfully been passed through the digital rx filter. this edge is th e potential beginning of a lin message frame. 5 initack initialization mode acknowledge ? initack indicates whether the slic module is in the reset mode as a result of writing initreq in slcc1. initack = 1 causes all slic register bits (except slcwcm: write once) to be held in their reset state and become not writable un til initack has been cleared. clear initack by clearing initreq in slcc1. after initack is cleared, the slic module pr oceeds to slic disabled mode (see figure 12-2 ) in which the other slic register bits are writ able and can be configured to the desired slic operating mode. initack is a read-only bit. 0 normal operation 1 slic module is in reset state 0 slcf slic interrupt flag ? the slcf interrupt flag indicates if a slic module interrupt is pending. if set, the slcsv is then used to determine what interrupt is pending. this flag is cleared by writing a 1 to the bit. if additional interrupt sources are pending, the bit will be automatically set to 1 again by the slic. 0 no slic interrupt pending 1 slic interrupt pending
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 198 freescale semiconductor read: any time write: ignored 12.3.5.1 lin mode operation table 12-8 shows the possible values for the possible sources for a slic interrupt while in lin mode operation (btm = 0). 76543210 r0 0 i 3i 2i 1i 0 0 0 w r e s e t00000000 = unimplemented or reserved figure 12-9. slic state vector register (slcsv) table 12-7. slcsv field descriptions field description 5:2 i[3:0] interrupt state vector ? these bits indicate the source of the interrupt request that is currently pending. table 12-8. interrupt sources summary (btm = 0) slcsv i3 i2 i1 i0 interrupt source priority 0x00 0 0 0 0 no interrupts pending 0 (lowest) 0x04 0 0 0 1 no-bus-activity 1 0x08 0 0 1 0 tx message buffer empty checksum transmitted 2 0x0c 0 0 1 1 tx message buffer empty 3 0x10 0 1 0 0 rx message buffer full checksum ok 4 0x14 0 1 0 1 rx data buffer full no errors 5 0x18 0 1 1 0 bit-error 6 0x1c 0 1 1 1 receiver buffer overrun 7 0x20 1 0 0 0 reserved 8 0x24 1 0 0 1 checksum error 9 0x28 1 0 1 0 byte framing error 10 0x2c 1 0 1 1 identifier received successfully 11 0x30 1 1 0 0 identifier parity error 12 0x34 1 1 0 1 reserved 13 0x38 1 1 1 0 reserved 14 0x3c 1 1 1 1 wakeup 15 (highest)
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 199 ? no interrupts pending this value indicates that all pending interrupt sources have been serviced. in polling mode, the slcsv is read and interrupts servi ced until this value reads back 0. this source will not generate an interrupt of the cpu, re gardless of state of slcie. ? no bus activity (lin specified error) the no-bus-activity condition occurs if no valid synch break field or byte field was received for more than 2 23 slic clock counts since the recept ion of the last valid message. for example, with 10 mhz slic clock frequency, a no-bus-activity interrupt will occur approximately 0.839 seconds after the bus begins to idle. ? tx message buffer empty ? checksum transmitted when the entire lin message frame has been transmitted successfully, complete with the appropriately selected checksum byte, this interrupt source is asserted. this source is used for all standard lin message frames and the final se t of bytes with extended lin message frames. ? tx message buffer empty this interrupt source indicates th at all 8 bytes in the lin messag e buffer have been transmitted with no checksum appende d. this source is used for intermediate sets of 8 bytes in extended lin message frames. ? rx message buffer full ? checksum ok when the entire lin message frame has been received successfully, complete with the appropriately selected checksum byte, and the checks um calculates correctly, this interrupt source is asserted. this source is used for all standard lin me ssage frames and the final set of bytes with extended lin message frames. to clear th is source, slcd0 must be read first. ? rx data buffer full ? no errors this interrupt source indicates that 8 bytes have been receiv ed with no checksum byte and are waiting in the lin message buffer. this source is used for inte rmediate sets of 8 bytes in extended lin message frames. to clear this source, slcd0 must be read first. ? bit error a unit that is sending a bit on the bus also monito rs the bus. a bit_error must be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. the slic will terminate the data transmission upon detection of a bi t error, according to the lin specification. bit errors are not checked when the lin bus is running at high speed due to the effects of physical layer round trip delay. b it errors are checked only when bedd = 0. ? receiver buffer overrun error this error is an indication that the receive buffe r has not been emptied and additional bytes have been received, resulting in lost data. because this interrupt is higher priority than the receive buffer full interrupts, it will appear first when an overflow condition occurs. th ere will, however, be a pending receive interrupt which must also be cleared after the buffer overrun flag is cleared. buffer overrun errors can be avoided if on reception of data complete with checksum correct (slcsv=$10) slcd0 is read, the software sets imsg after recepti on of a valid id, the software enters btm mode, or received data caus es a framing or checksum error to occur. ? checksum error (lin specified error) the checksum error occurs when the calculated checksum value does not match the expected value. if this error is encountered, it is important to verify that the correct checksum calculation
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 200 freescale semiconductor method was employed for this message frame. refe r to the lin specification for more details on the calculations. ? byte framing error this error comes from the standard uart defini tion for byte encoding and occurs when the stop bit is sampled and reads back as a 090. stop should always read as 1. note a byte framing error can also be an indication that the number of data bytes received in a lin message frame does not match the value written to the slcdlc register. see section 12.6.7, ?handling lin message headers ,? for more details. ? identifier received successfully this interrupt source indicates that a lin identifi er byte has been received with correct parity and is waiting in the lin identifier buffer (slcid). upon reading this interrupt source from slcsv, the user can then decode the identifier in soft ware to determine the nature of the lin message frame. to clear this source, slcid must be read. ? identifier-parity-error a parity error in the identifier (i.e., corrupt ed identifier) will be flagged. typical lin slave applications do not distinguish between an unknown but valid identifi er, and a corrupted identifier. however, it is mandatory for all slave nodes to evalua te in case of a known identifier all eight bits of the id-field and distinguish between a known and a corrupted iden tifier. the received identifier value is reported in slcid so that the user softwa re can choose to acknowle dge or ignore the parity error message. once the id parity error has been detected, the slic will begin looking for another lin header and will not receive messag e data, even if it appears on the bus. ? wakeup the wakeup interrupt source indicates that th e slic module has entered slic run mode from slic stop mode. 12.3.5.2 byte transfer mode operation when byte transfer mode is enabled (btm = 1), ma ny of the interrupt sources for the slcsv no longer apply, as they are specific to lin operations. table 12-9 shows those interrupt sources which are applicable to btm operations . the value of the slcsv for each interr upt source remains the same, as well as the priority of the interrupt source. i table 12-9. interrupt sources summary (btm = 1) slcsv i3i2i1i0 interrupt source priority 0x00 0000 no interrupts pending 0 (lowest) 0x0c 0011 tx mess age buffer empty 3 0x14 0101 rx data buffer full no errors 5 0x18 0110 bit-error 6 0x1c 0111 receiver buffer overrun 7
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 201 ? no interrupts pending this value indicates that all pending interrupt sources have been serviced. in polling mode, the slcsv is read and interrupts servi ced until this value reads back 0. this source will not generate an interrupt of the cpu, re gardless of state of slcie. ? tx message buffer empty in byte transfer mode, this interrupt source indicates that the byte in the slcid has been transmitted. ? rx data buffer full ? no errors this interrupt source indicates th at a byte has been received and is waiting in slcid. to clear this source, slcid must be read first. ? bit error a unit that is sending a bit on the bus also monito rs the bus. a bit_error must be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. the slic will terminate the data transmission upon detection of a bi t error, according to the lin specification. bit errors are not checked when the lin bus is running at high speed due to the effects of physical layer round trip delay. b it errors are checked only when bedd = 0. ? receiver buffer overrun error this error is an indication that the receive buffe r has not been emptied a nd additional byte(s) have been received, resulting in lost data. because this interrupt is higher priority than the receive buffer full interrupts, it will appear first when an overflow condition occurs. th ere will, however, be a pending receive interrupt which must also be cleared after the buffer overrun flag is cleared. buffer overrun errors can be avoided if on reception of data (slcsv=$14) sl cd0 is read or received data causes a framing error to occur. ? byte framing error this error comes from the standard uart definition for byte encoding and occurs when stop is sampled and reads back as a 0. stop should always read as 1. a byte framing error could be encountered if the bit timing value programmed in bth:l does not match the bit rate of the incoming data. ? ? wakeup the wakeup interrupt source indicates that th e slic module has entered slic run mode from slic wait mode. 0x28 1010 byte framing error 10 0x38 1110 reserved 14 0x3c 1111 wakeup 15 (highest) table 12-9. interrupt sources summary (btm = 1) slcsv i3i2i1i0 interrupt source priority
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 202 freescale semiconductor 12.3.6 slic data length code register (slcdlc) the slic data length code register (slcdlc) is the primary functiona l control register for the slic module during normal lin operations. it contains the data length code of the message buffer, indicating how many bytes of data are to be sent or received, as well as the checksum m ode control and transmit enabling bit. 76543210 r txgo chkmod dlc5 dlc4 dlc3 dlc2 dlc1 dlc0 w r e s e t00000000 figure 12-10. slic data length code register (slcdlc) table 12-10. slcdlc field descriptions field description 7 txgo slic transmit go ? this bit controls whether the slic module is sending or receiving data bytes. this bit is automatically reset to 0 after a transmit operation is co mplete or an error is encountered and transmission has been aborted. 0 slic receive data 1 initiate slic transmit? the slic assumes the user has loaded the proper data into the message buffer and will begin transmitting the number of bytes indicated in the slcdlc bits. if the number of bytes is greater than 8, the first 8 bytes will be transmitted and an interrupt wil l be triggered (if unmasked) for the user to enter the next bytes of the message. if the number of bytes is 8 or fewer, the slic will transmit the appropriate number of bytes and automati cally append the checksum to t he transmission. if imsg or txabrt are set or the slcf flag is set, writes to txgo will have no effect. 6 chkmod lin checksum mode ? chkmod is used to decide what checksum method to use for this message frame. resets after error code or message frame complete. chkmod must be written (124 desired) only after the reception of an identifier and before the reception or transmission of data byte s. writing this bit to a one clears the current checksum calculation. 0 checksum calculated 119 the identifier byte included (sae j2602/lin 2.0) 1 checksum calculated without the identifier byte (lin spec <= 1.3) 5:0 dlc data length control bits ? the value of the bits indicate the nu mber of data bytes in message. values 0x00?0x07 are for ?normal? lin messaging. values 0x08?0x3f are for ?extended? lin messaging. see ta b l e 1 2 - 1 1 . table 12-11. data length control dlc[5:0] message data length (number of bytes) 0x00 1 0x01 2 0x02 3 ... ... 0x3d 62 0x3e 63 0x3f 64
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 203 12.3.7 slic identifier and data registers (slcid, slcd7-slcd0) the slic identifier (slcid) and ei ght data registers (slcd7?slcd0) co mprise the transmit and receive buffer and are used to read/write th e identifier and message buffer 8 d ata bytes. in btm mode (btm = 1), only slcid is used to send and receive bytes, as only one byte is ha ndled at any one ti me. the number of bytes to be read from or written to these registers is determined by the user software and written to slcdlc. to obtain proper data, reads and writes to these registers must be made based on the proper length corresponding to a particular message. it is the re sponsibility of the user so ftware to keep track of this value to prevent data corruption. for example, it is possible to read data fr om locations in the message buffer which contain erroneous or old data if the user software reads mo re data registers than were updated by the incoming message, as indicated in slcdlc. note an incorrect length value written to slcd lc can result in the user software misreading or miswriting data in the message buffer. an incorrect length value might also result in slic erro r messages. for example, if a 4-byte message is to be received, but the user software incorrect ly reports a 3-byte length to the dlc, the slic will a ssume the 4th data byte is actually a checksum value and attempt to validate it as such. if this value doesn?t match the calculated value, an incorrect checksum error will occur. if it does happen to match the expected value, then the message would be received as a 3-byte message with valid checksum. ei ther case is incorrect behavior for the application and can be avoided by ensuring that the correct length code is used for each identifier. the first data byte received after the lin identifier in a lin mess age frame will be loaded into slcd0. the next byte (if applicab le) will be loaded into slcd1, and so forth. the slic identifier register is used to capture the incoming lin identifier and when the slcsv value indicates that the identifier has been received successfully, this register contains the received identifier value. if the incoming identifier contained a parity erro r, this register value wi ll not contain valid data. in byte transfer mode (btm = 1), th is register is used for sending a nd receiving each byte of data. when transmitting bytes, the data is loaded into this regi ster, then txgo in slcdlc is set to initiate the transmission. when receiving bytes, they are read from this register only. 76543210 rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 r e s e t00000000 figure 12-11. slic identifier register (slcid)
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 204 freescale semiconductor r ? read slc receive data t ? write slc transmit data 12.4 functional description the slic provides full standard lin message buffe ring for a slave node, minimizing the need for cpu intervention. routine protocol functions (such as synchronization to th e communication channel, reception, and verification of header data) and gene ration of the checksum are handled automatically by the slic. this allows application software to be greatly simplified relative to standard uart implementations, as well as reducing the impact of interrupts needed in those applicati ons to handle each byte of a message independently. additionally, the slic has the ability to automatically synchronize to any lin message, regardless of the lin bus bit rate (1?20 kbps), properly receiving that message without prior programming of the target lin bit rate. furthermore, this can even be accomplished using an untrimmed internal oscillator, provided its accuracy is at least 50% of nominal. the slic also has a simple uart-like byte transfer mode, which allows the user to send and receive single bytes of data in half-duplex 8-n-1 format (8-bit data , no parity, 1 stop bit) wi thout the need for lin message framing. 12.5 interrupts the slic module contains one interrupt vector, whic h can be triggered by sources encoded in the slic state vector register. see section 12.3.5, ?slic state vector register (slcsv) .? 12.5.1 slic during break interrupts the bcfe bit in the bscr register has no affect on the slic module. therefore the slic modules status bits cannot be protected during break. 12.6 initialization/application information the lin specification defines a st andard lin ?message fr ame? as the basic format for transferring data across a lin network. a standard message frame is composed as shown in figure 12-13 (shown with 8 data bytes). lin transmits all data, identifier, and checksum characters as standard uart characters with eight data bits, no parity, and one stop bit. therefore, each byte has a length of 10 bits, including the start and stop bits. the data bits are transmitted least significant bit (lsb) first. 76543210 rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 reset00000000 figure 12-12. slic data register x (slcd7?slcd0)
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 205 figure 12-13. typical lin message frame 12.6.1 lin message frame header the header section of all lin mess ages is transmitted by the master node in the network and contains synchronization data, as well as the identifier to define what information is to be contained in the message frame. formally, the header is comprised of three parts: 1. synch break 2. synch byte (0x55) 3. identifier field the first two components are present to allow the lin slave nodes to recogni ze the beginning of the message frame and derive the bi t rate of the master module. the synch break allows the slave to see the be ginning of a message frame on the bus. the slic module can receive a standard 10-bi t break character for the synch br eak, or any break symbol 10 or more bit times in length. this encompasses the lin requirement of 13 or more bits of length for the synch break character. the synch byte is always a 0x55 data byte, providing fi ve falling edges for the slave to derive the bit rate of the master node. the identifier byte indicates to the slave what is the nature of the data in the message frame. this data might be supplied from either the ma ster node or the slave node, as determ ined at system design time. the slave node must read this identifier, check for parity errors, and determine whether it is to send or receive data in the data field. more information on the header is contained in section 12.6.7.1, ?lin message headers .? 12.6.2 lin data field the data field is comprised of standard bytes (eight data bits, no pari ty, one stop bit) of data, from 0?8 bytes for normal lin frames and greater than eight bytes for extended lin frame s. the slic module will either transmit or receive these by tes, depending upon the user code inte rpretation of the identifier byte. data is always tran smitted into the data field l east significant byte (lsb) first. the slic module can automatically handle up to 64 bytes in extended lin message frames without significantly changing program execution. synch break synch byte ident field data field data field data field data field data field data field data field checksum field data field 01 2345 67 0x55 13 or more bits (lin 1.3) header data
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 206 freescale semiconductor 12.6.3 lin checksum field the checksum field is a data integrity measure for li n message frames, used to signal errors in data consistency. the lin 1.3 checksum calculation only covers the data field, but the slic module also supports an enhanced checksum calcul ation which also includes the iden tifier field. for more information on the checksum calculation, refer to section 12.6.13, ?lin data integrity checking methods .? 12.6.4 slic module constraints in designing a practical modul e, certain reasonable c onstraints must be placed on the lin message traffic which are not necessarily explicitl y specified in the lin specification. the slic module presumes that: ? timeout for no-bus-activity = 1 second. 12.6.5 slcsv interrupt handling each change of state of the slic m odule is encoded in the slic state vect or register (slcsv). this is an efficient method of handling state cha nges, indicating to the user not only the current status of the slic module, but each state change will also generate an interrupt (if slic interrupt s are enabled). for more detailed information on th e slcsv, please refer to section 12.3.5, ?slic state ve ctor register (slcsv) .? in the software diagrams in the fo llowing subsections, when an interr upt is shown, the first step must always be reading slcsv to determine what is the cu rrent status of the slic module. likewise, when the diagrams indicate to ?exit isr?, the final step to exi ting the interrupt service rou tine is to clear the slcf interrupt flag. this can only be done if the slcsv has first been read, a nd in the case that data has been received (such as an id byte or command message data) the slcd has been read at least one time. after slcsv is read, it will switch to the next pending state, so the user must be sure it is copied only once into a software variable at the beginning of the inte rrupt service routine to avoid inadvertently clearing a pending interrupt source. additional decisions based on this value must be made from the software variable, rather than from the slcsv itself. after exiting the isr, normal application code may resume. if the diagram indicates to ?return to idle,? it indicates that all processi ng for the current message frame has been completed. if an error was detected and the corresponding error code loaded into th e slcsv, any pending data in the data buffer will be flushed out and the slic returned to its idle state, seeking out the next message frame header. 12.6.6 slic module initialization procedure 12.6.6.1 lin mode initialization the slic module does not require very much initializ ation, due to its self-sync hronizing design. because no prior knowledge of the bit rate is required to synchronize to the li n bus, no programming of bit rate is required. at initialization time, th e user must configure: ? slic prescale register (slic dig ital receive filter adjustment). ? wait clock mode operation.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 207 the slic clock is the same as the cpu bus clock. th e module is designed to provide better than 1% bit rate accuracy at the lowest value of the slic clock frequency and the accuracy improves as the slic clock frequency is increased. for this reas on, it is advantageous to choose the fastest slic clock which is still within the acceptable operating range of the slic.because the slic may be used wi th mcus with internal oscillators, the tolerance of the oscillator must be taken into account to ensure that slic clock frequency does not exceed the bounds of the slic clock operating range. this is especially important if the user wishes to use the oscillator untrimmed, where proces s variations might result in mcu frequency offsets of 25%. the acceptable range of slic clock frequencies is 2 to 20 mhz to gua rantee lin operations with greater than 1.5% accuracy across the 1?20 kbps range of lin bi t rates. the user must ensure that the fastest possible slic clock frequency neve r exceeds 20 mhz or that the slowes t possible slic clock never falls below 2 mhz under worst case conditions. this woul d include, for example, oscillator frequency variations due to untrimmed oscill ator tolerance, temperature varia tion, or supply voltage variation. to initialize the slic module into lin operating mode, the user must perform the following steps prior to needing to receive any lin message traffic. thes e steps assume the mcu has been reset either by a power-on reset (por) or any other mcu reset mechanism. the steps for slic initiali zation for lin operation are: 1. write slcc1 to clear initreq. 2. when initack = 0, write slcc1 & slcc2 with desired values for: a) slcwcm ? wait clock mode. 3. write slcc2 to set up prescalers for: a) rxfp ? digital receive filter clock prescaler. 4. enable the slic module by writing slcc2: a) slce = 1 to place slic module into run mode. b) btm = 0 to disable byte transfer mode. 5. write slcc1 to enable slic interrupts (if desired). 12.6.6.2 byte transfer mode initialization bit rate synchronization is handled automatically in lin mode, using the sync hronization data contained in each lin message to derive the desired bit rate. in byte transfer mode (btm = 1); however, the user must set up the bit rate fo r communications using slcbt. more information on byte transf er mode is described in section 12.6.16, ?byte transfer mode operation ,? including the performance parameters on recomme nded maximum speeds, bit time resolution, and oscillator tolerance requirements. after the desired settings of bit time are determined , the slic initialization fo r btm operation is virtually identical to that of lin operation. the steps are: 1. write slcc1 to clear initreq.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 208 freescale semiconductor 2. when initack = 0, write slcc 2 with desired values for: a) slcwcm ? wait clock mode. 3. write slcc2 to set up: a) rxfp ? digital receive filter clock prescaler. 4. enable the slic module by writing slcc2: a) slce = 1 to place slic module into run mode. b) btm = 1 to enable byte transfer mode. 5. write slcbt value. 6. write slcc1 to enable slic interrupts (if desired). note the slic module is designed primarily for use in lin sy stems and assumes the connection of a lin transceiver, wh ich provides a resistive path between the transmit and receive pins. btm m ode will not operate properly without a resistive feedback path between slctx and slcrx. 12.6.7 handling lin message headers figure 12-14 shows how the slic module deals with incoming lin message headers.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 209 figure 12-14. handling lin message headers 12.6.7.1 lin message headers all lin message frame headers ar e comprised of three components: ? the first is the synchronization break (s ynch break) symbol, which is a dominant (low) pulse at least 13 or more bit times long, followed by a recessive (high) synchronization delimiter of at least one bit time. in lin 2.0, this is allowed to be 10 or more bit times in length. ? the second part is called the synchronization field (synch field) and is a single byte with value 0x55. this value was chosen as it is the only one which pr ovides a series of five falling (recessive to dominant) transitions on the bus. process error code: lin message header received slic updates slcbt id arriving in rx buffer n y error code ? y n id for this ? n y node interrupt process valid id byte framing error process error code: identifier-parity error set imsg bit byte framing error exit isr return to read id from slcid read slcsv lin bus idle valid break and synch data? interrupt read slcsv clear slcf clear slcf clear slcf
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 210 freescale semiconductor ? the third section of the message frame header is the identifier field (id). the identifier is covered more in section 12.6.8, ?handling command message frames ,? and section 12.6.9, ?handling request lin message frames .? the slic automatically reads the incoming patt ern of the synchronization break and field and determines the bit rate of the lin data frame, as well as checking for errors in form and discerning between a genuine break/field combination and a s imilar byte pattern somewhere in the data stream. after the header has been verified to be valid and has been processed, the slic module updates the slic bit time register (slcbt) with th e value obtained from the synch field and begins to receive the id. after the id for the message frame ha s been received, an interrupt is gene rated by the slic and will trigger an mcu interrupt request if unmaske d. at this point, it might be possi ble that the id was received with errors such as a parity error (based on the lin specific ation) or a byte framing error. if the id did not have any errors, it will be copied into the slcd for the so ftware to read. the slcsv will indicate the type error or that the id wa s received correctly. in a lin system, the meaning and function of all messages, and therefore all message identifiers, is pre-defined by the system designer. this information ca n be collected and stored in a standardized format file, called a configuration language description (cld) file. in usi ng the slic module, it is the responsibility of the user software to determine the nature of th e incoming message, and therefore how to further handle that message. the simplest case is when the slic r eceives a message which the user softwa re determines is of no interest to the application. in other words, the slave node does not need to receive or transmit any data for this message frame. this might also apply to messages with zero data byt es (which is allowed by the lin specification). at this point, the user can set the imsg control bit, and ex it the interrupt service routine by clearing the slcif flag. because there is no data to be se nt or received, the slic will not generate another interrupt until the next message frame header or bus goes idle long enough to trigger a ?no-bus-activity? error according to the lin specification. note imsg will prevent another interrupt fr om occurring for the current message frame; however, if data bytes are appe aring on the bus they may be received and copied into the message buffer. this will delete any previous data which might have been present in the buffer, even though no interrupt is triggered to indicate the arrival of this data. at the time the id is read, the user might also choose to read slcbt and copy this value out to an application variable. th is data can then be used at a time appropr iate to both the appl ication software and the lin communications to adjust the trim of the inte rnal oscillator. this opera tion must be handled very carefully to avoid adjusting the base timing of the mcu at the wr ong time, adversely affecting the operation of the slic module or of the application itself. more inform ation about this is contained in section 12.6.17, ?oscillator trimming with slic .? if the user software determines th at the id read out of the slcd corresponds to a command or request message for which this node needs to receive or tr ansmit data (respectively) , it will then move on to procedures described in section 12.6.8, ?handling command message frames ,? and section 12.6.9, ?handling request lin message frames .?
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 211 for clarification, in this document, ?command? messages will refer to any message frame where the slic module is receiving data bytes and ?request? messages refer to messag e frames where the slic module will be expected to transmit data bytes. this is a generic description a nd should not be confused with the terminology in the lin specification. the lin use of the terms ?command? and ?r equest? have the same basic meaning, but are limite d in scope to specific iden tifier values of 0x3c a nd 0x3d. in the slic module documentation, these terms have been used to describe these functional types of messages, regardless of the specific identifier value used. 12.6.7.2 possible errors on message headers possible errors on message headers are: ? identifier-parity-error ? byte framing error 12.6.8 handling command message frames figure 12-15 shows how to handle command message frames, where the slic module is receiving data from the master node. command message frames refer to lin messages fr ames where the master node is ?commanding? the slave node to do something. the impli cation is that the slave will then be receiving data from the master for this message frame. this can be a standard lin message frame of 1?8 data bytes, a reserved lin system message (using 0x3c identifier), or an extended command message frame utilizing the reserved 0x3e user defined identifier or perhaps the 0x3f lin reserved extended identifier. the slic module is capable of handling message frames containing up to 64 bytes of data, wh ile still automatically calculating and/or verifying the checksum. 12.6.8.1 standard command message frames after the application software has read the incoming iden tifier and determined that it is a valid identifier which cannot be ignored using imsg, it must determ ine if this message frame is a command message frame or a request message frame. (i.e., should the appl ication receive data from the master or send data back to the master?) the first case, shown in figure 12-15 deals with command messages, wh ere the slic will be receiving data from the master node. if the received identifier corresponds to a standard lin command frame (i.e., 1?8 data bytes), the user must then write the numbe r of bytes (determined by the system designer and directly linked with this particular identifier) corresponding to the length of the message frame into slcdlc. the two most significant bits of this regist er are used for special control bits describing the nature of this message frame.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 212 freescale semiconductor figure 12-15. handling command messages (data receive) the slic transmit go (txgo) bit should be 0 for command frames, i ndicating to the slic that data is coming from the master. the checksum mode control (chkmod ) bit allows the user to select which method of checksum calculation is desired for this message frame. the lin 1.3 checksum does not include the identifier byte in the calculati on, while the sae version does include this byte. because the identifier is already received by the slic by this time, the de fault is to include it in the calculation. if a lin 1.3 checksum is desired, a 1 in chkmod will reset the chec ksum circuitry to begin calculating the checksum command message ? process valid id n y initialize sw byte count process request message extended frame ? y n write slcdlc for this id 0nxx xxxx (txgo = 0) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle 1. empty rx buffer 2. decrement sw byte count by 8 last frame ? y n (sw byte count < 8) write slcdlc for this id 0n00 0xxx (txgo = 0) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle empty rx buffer byte framing error checksum-error no-bus-activity byte framing error no-bus-activity interrupt read slcsv interrupt read slcsv receive buffer overrun receive buffer overrun clear slcf 3. clear slcf clear slcf clear slcf
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 213 on the first data byte. using chkmod in this way allows the slic to receive messages with either method of data consistency check and change on a fr ame-by-frame basis. if a system uses both types of data consistency checking methods, th e software must simply change th e setting of this bit based on the identifier of each message. if the network only uses one type of check, chkmod can be set as a constant value in the user?s code. if chkmod is not written on each frame, care mu st be taken not to accidentally modify the bit when writing the data length and txgo bits. this is especially true if using c code without carefully inspecting the output of the compiler and assembler. the control bits and data length code are contained in one register, allowing the user to maximize the efficiency of the identifier proce ssing by writing a single byte value to indicate the nature of the message frame. this allows very efficient identifier proces sing code, which is important in a command frame, as the master node can be sendi ng data immediately following the identif ier byte which might be as little as one byte in length. the slic module us es a separate internal storage area for the incoming data bytes, so there is no danger of losing incoming data, but the user should spend as little time as possible within the isr to ensure that the applicatio n or other isrs are able to use the majority of the cpu bandwidth. the identifier must be processed in a maximum of 2 byte times on the lin bus to ensure that the isr completes before the checks um would be received for the shortest possible message. this should be easily achievable, as the only operations required are to read slcid and look up the checksum method, data length, and command/request state of that identifier, then write that value to the slcdlc. this can be easily streamlined in code with a lookup tabl e of identifiers and co rresponding slcdlc bytes. note once the id is decoded for a message header and a length code written to slcdlc, the slic is expecting that number of bytes to be received. if the slic module doesn't receive the number of bytes indicated in the slcdlc register, it will continue to look for data bytes. if another message header begins, a byte framing error will trigge r on the break symbol of that second message. the second message will still properly generate an id received interrupt, but the byte framing error prio r to this is an indication to the application that the previous message was not properly handled and should be discarded. 12.6.8.2 extended command message frames handling of extended frames is very similar to handl ing of standard frames, pr oviding that the length is less than or equal to 64 bytes. because the slic mo dule can only receive 8 bytes at a time, the receive buffer must be emptied periodically for long message frames. this is not standard lin operation, and is likely only to be used for downloading calibration data or reprogrammi ng flash devices in a factory or service facility, so the added steps required for processing are not as crit ical to performance. during these types of operations, the application c ode is likely very limited in sc ope and special adjustments can be made to compensate for added message processing time. for extended command frames, the data length is still written one time at the time the identifier is decoded, along with the txgo and chkm od bits. when this is done, a software counter must also be initialized to keep track of how many bytes are expected to be received in the message frame. the isr completes, clearing the slcf flag, and resume s application execution. the slic will generate an interrupt, if
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 214 freescale semiconductor unmasked, after 8 bytes are received or an error is detected. at this interrupt, the slcsv will indicate an error condition (in case of byte framing error, idle bus) or that the receive buffer is full. if the data is successfully received, the user must then empty the buffer by reading slcd7-slcd 0 and then subtract 8 from the software byte count. when th is software counter reaches 8 or fe wer, the remaining data bytes will fit in the buffer and only one interrupt should occur. at this time, the final interrupt may be handled normally, continuing to use the soft ware counter to read the proper number of bytes from the appropriate slcd registers. note do not write slcdlc more than one time per lin message frame. the slic tracks the number of sent or re ceived bytes based on the value written to this register at the beginning of the data field and rewrit ing this register will corrupt the checksum calculation and cause unpredictable behavior in the slic module. the application soft ware must track the number of sent or received bytes to know what the current byte count in the slic is. if programming in c, make sure to use the volatile modifier on this variable (or make it a global variable ) to ensure that it keeps its value between interrupts. 12.6.8.3 possible errors on command message data possible errors on command message data are: ? byte framing error ? checksum-error (lin specified error) ? no-bus-activity (lin specified error) ? receiver buffer overrun error 12.6.9 handling request lin message frames figure 12-16 shows how to handle request me ssage frames, where the slic module is sending data to the master node. request message frames refer to li n messages frames where the master node is ?requesting? the slave node to supply information. the implication is that the slave will th en be transmitting data to the master for this message frame. this can be a standard lin message frame of 1?8 data bytes, a reserved lin system message (using 0x3d identifier), or an extended request message frame utiliz ing the reserved 0x3e identifier or perhaps the 0x3f lin reserved extended identifier. the slic module is capable of handling request message frames containing up to 64 bytes of data, while still automatically calculating and/or verifying the checksum. 12.6.9.1 standard request message frames dealing with request messages with th e slic is very similar to deali ng with command messages, with one important difference. because the slic is now to be transmitting data in the lin message frame, the user software must load the data to be transmitted into the message buffer prior to initiating the transmission.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 215 this means an extra step is taken inside the interrupt service routine after the identifier has been decoded and is determined to be an id for a request message frame. figure 12-16 deals with request messages, wh ere the slic will be transmitti ng data to the master node. if the received identifier corresponds to a standard li n command frame (i.e., 1-8 data bytes), the message processing is very simple. th e user must load the data to be transm itted into the transmit buffer by writing it to the slcd registers. the first byte to be transm itted on the lin bus must be loaded into slcd0, then slcd1 for the second byte, etc. after all of the bytes to be transmitted are loaded in this way, a single write to slcdlc will allo w the user to encode the number of data bytes to be transmitted (1?8 bytes for standard request frames), set the pr oper checksum calculation method fo r the data (chkmod), as well as signal the slic that the buffer is re ady by writing a 1 to t xgo. txgo will remain se t to 1 until the buffer is sent successfully or an error is encountered, signaling to th e application code that the buffer is in process of transmitting. in cases of 1?8 data bytes only bei ng sent (standard lin request frames), the slic automatically calculates and transmit s the checksum byte at the end of the message frame. the user can exit the isr after slcdlc has been writte n and the slcf flag has been cleared.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 216 freescale semiconductor figure 12-16. handling request lin message frames the next slic interrupt which occu rs, if unmasked, will indicate the e nd of the request message frame and will either indicate that the frame was properly transmitted or that an error was encountered during transmission. refer to section 12.6.9.4, ?possible errors on request message data ,? for more detailed explanation of these pos sible errors. this interrupt also signals to the application that the message frame is complete and all data bytes and the checksum value have been properly transmitted onto the bus. process request message extended frame ? y n 4. write slcdlc for this id 1nxx xxxx (txgo = 1) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle decrement sw byte count by 8 last frame ? y n (sw byte count <8) 3. write slcdlc for this id 1n00 0xxx (txgo = 1) (chkmod = n) exit isr error code ? y n process error code: exit isr return to idle transmit complete 2. initialize sw byte count 3. load first 8 data bytes 2. load data into message buffer 1. load last ( < 8) bytes to transmit byte framing error bit-error checksum-error byte framing error bit-error interrupt read slcsv interrupt read slcsv 2. write txgo bit to start transmit (1) 1. load next 8 bytes to transmit 2. write txgo bit to start transmit (1) note 1. when writing txgo bit only, ensure that chkmod and data length values are not accidentally modified. 1. clear slcf 1. clear slcf clear slcf clear slcf clear slcf clear slcf
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 217 the slic module cannot begin to transm it the data until the user writes a 1 to txgo, indicating that data is ready. if the user writ es txgo without loading data into the transmit buffer, wh atever data is in storage will be transmitted, where the number of bytes transmitted is based on the data length value in the data length register. similarly, if the us er writes the wrong value for the numbe r of data bytes to transmit, the slic will transmit that number of bytes, potentially tran smitting garbage data on to the bus. the checksum calculation is performed based on the data tran smitted, and will theref ore still be calculated. the identifier must be processed, data must be load ed into the transmit buffer, and the slcdlc value written to initiate data transmissi on in a certain amount of time, based on the lin spec ification. if the user waits too long to start transmission, the master node will observe an idle bus and trigger a slave not responding error condition. the same er ror can be triggered if the tran smission begins too late and does not complete before the message frame times out. refer to the lin specification for more details on timing constraints and requirements for lin slave devices. this is especially important when dealing with extended request frames, when the data must be loaded in 8 byte sections (maximum) to be transmitted at each interrupt. 12.6.9.2 extended reque st message frames handling of extended frames is very similar to handl ing of standard frames, pr oviding that the length is less than or equal to 64 byt es. because the slic module can only transmit 8 bytes at a time, the transmit buffer must be loaded periodically for extended message frames. this is not st andard lin operation, and is likely only to be used for special cases, so th e added steps required for processing should not be as critical to performance. during thes e types of operations, the application code is likely very limited in scope and special adjustments can be made to compensate for added message processing time. when handling extended request frames , it is important to clear the slcf flag first, before loading any data or writing txgo. the data lengt h is still written only one time, at the time the identifier is decoded, along with the txgo and chkmod bits, after the first 8 data bytes are loaded into the transmit buffer. when this is done, a software counter must also be initialized to keep track of how many bytes are to be transmitted in the message frame. the slic will generate an interrupt, if unmasked, after 8 bytes are transmitted or an error is detected. at this interrupt, the slcsv will indicate an error condition (in case of byte framing error or bit erro r) or that the transmit buffer is empty. if the data is transmitted successfully, the user must then clear the slcf fl ag, subtract 8 from the software byt e count, load the next 8 bytes into the slcd registers, and write a 1 to txgo to tell the slic that the buffers are loaded and transmission can commence. when this software c ounter reaches 8 or fewer, the rema ining data bytes will fit in the transmit buffer and the slic will au tomatically append the ch ecksum value to the fr ame after the last byte is sent.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 218 freescale semiconductor note do not write the chkmod or data length values in slcdlc more than one time per message frame. the slic tracks the number of sent or received bytes based on the value written to this register at the beginning of the data field and rewriting this register will corrupt th e checksum calculation and cause unpredictable behavior in the sl ic module. the application software must track the number of sent or recei ved bytes to know what the current byte count in the slic is. if program ming in c, make sure to use the static modifier on this variable (or make it a global variable) to ensure that it keeps its value between interrupts. 12.6.9.3 transmit abort the transmit abort bit (txabrt) in slcc1 allows the user to cease tr ansmission of data on the next byte boundary. when this bit is set to 1, it will finish transmitting the byt e currently being transmitted, then cease transmission. after th e transmission is successfully aborted, txabrt will automa tically be reset by the slic to 0. if the slic is not in process of tran smitting at the time txabrt is written to 1, there is no effect and txabrt will read back as 0. 12.6.9.4 possible errors on request message data possible errors on request message data are: ? byte framing error ? checksum-error (lin specified error) ? bit-error 12.6.10 handling imsg to minimize interrupts the imsg feature is designed to minimize the number of interrupts required to maintain lin communications. on a netw ork with many slave nodes, it is very likely that a particular slave will observe messages which are not intended for that node. when the slic module detects any message header, it synchronizes to that message frame and bit rate, then interrupts the cpu after the identifier byte has been successfully received and parity chec ked. at this time, if the software determines that the message may be ignored, imsg may be set to indicate to the module that the data field of the message frame is to be ignored and no additional interrupts s hould be generated until the next valid message header is received. the bit is automatically reset to 0 after the cu rrent message frame is complete and the lin bus returns to idle state. this reduces the load on the cpu and allows the ap plication software to im mediately begin performing any operations which might otherwise not be allowed while receiving messaging. note imsg will prevent another interrupt fr om occurring for the current message frame, however if data byt es are appearing on the bus they may be received and copied into the message buffer. this will delete any previous data which might have been present in the buffer, even though no interrupt is triggered to indicate the arrival of this data.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 219 12.6.11 sleep and wakeup operation the slic module itself has no special sleep mode , but does support low-power modes and wake-up on network activity. for low-power operations, the user mu st select whether or not to allow the slic clock to continue operating when the mcu issues a wa it instruction through the slc wait clock mode (slcwcm) bit in slcc1. if slcwcm = 1, the slic will enter slic stop mode when the mcu executes a wait instruction. if slcwcm = 0, the sl ic will enter slic wait mode when the mcu executes a wait instruction. for more information on th ese modes, as well as wakeup options from these modes, please refer to section 12.1.2, ?modes of operation .? when network activity occurs, the slic module will wa ke the mcu out of stop or wait mode, and return the slic module to slic run mode. if the slic was in slic wait mode, normal slic interrupt processing will resume. if the slic was in sl ic stop mode, slcsv will indicate wakeup as the interrupt source so that the user knows that the slic module brought the mcu out of stop or wait. in a lin system, a system message is generally sent to all nodes to indicat e that they are to enter low-power network sleep mode. after a node enters sleep mode, it waits for outside events, such as switch or sensor inputs or network traffic to bring it out of network sleep mode. if the node using the slic module is awakened by a source other than networ k traffic, such as a switch input, the lin specification requires this node to issue a wake-up signal to the rest of the ne twork. the slic module supports this feature using waketx in slcc2. the user software may set this bit and one lin wake-up signal is immediately transmitted on the bus, then the bit is automatically cleared by the slic module. if another wake-up signal is required to be sent, the user must set waketx again. the waketx function was designed for highest flexibility, but is generally useful for lin 2.0 or later versions. older lin wakeup messages can be supported using btm mode (i.e. to send the 0x80 wake up character from an earlier version of lin). in a lin system, the lin physical interface ca n often also provide an output to the irq pin to provide a wake-up mechanism on network activity. the physical la yer might also control voltage regulation supply to the mcu, cutting power to the mc u when the physical layer is placed in its low-power mode. the user must take care to ensure that the interaction between the physical layer, irq pin, slic transmit and receive pins, and power supply regulator is fully unde rstood and designed to ensure proper operation. 12.6.12 polling operation it is possible to operate the slic module in polling mode, if desired. the primary difference is that the slic interrupt request should not be enabled (slcie = 0). the slcs v will update and operate properly and interrupt requests will be indicated with the slcf flag, which can be polled to determine status changes in the slic module. it is required that the pol ling rate be fast enough to ensure that slic status changes be recognized and processed in time to ensure that all application timings can be met. 12.6.13 lin data integr ity checking methods the slic module supports two differen t lin-based data integrity options: ? the first option supports lin 1.3 and older methods of checksum calculations. ? the second option supports an optional additional enhanced checksum calculation which has greater data integrity coverage.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 220 freescale semiconductor the lin 1.3 and earlier specificati ons transmit a checksum byte in the ?checksum field? of the lin message frame. this checksum fi eld contains the inverted modul o-256 sum over all data bytes. the sum is calculated by an ?add with carry? where the carry bit of each additi on is added to the least significant bit (lsb) of its resulting sum. this guarantees security al so for the msbs of the data bytes. the sum of modulo-256 sum over all data bytes and the checksum byte must be ?0xff?. an optional checksum calculation can also be performed on a lin data fra me which is very similar to the lin 1.3 calculation, but with one important distinction. this enhanced calculation simply includes the identifier field as the first value in the calculation, whereas the lin 1.3 calculati on begins with the least significant byte of the data field (w hich is the first byte to be tran smitted on the bus). this enhanced calculation further ensures th at the identifier field is correct and ties the identifier and data together under a common calculation, ensuring greater reliability. in the slic module, either checksum calculation can be performed on any given message frame by simply writing or clearing chkmod in sl cdlc, as desired, when the identi fier for the message frame is decoded. the appropriate calculation for each message frame should be decided at system design time and documented in the lin description fi le, indicating to the user which cal culation to use for a particular identifier. 12.6.14 high-speed lin operation high-speed lin operation does not necessarily requ ire any reconfiguration of the slic module, depending upon what maximum lin bit rate is desired. several factors affe ct the performance of the slic module at lin speeds higher th an 20 kbps, all of which are functions of the speed of the slic clock and the prescaler of the digita l filter. the tightest constr aint comes from the need to maintain 1.5% accuracy with the master node timing. this requires that the slic module be able to sample the incoming data stream accurately enough to guarantee that accuracy. table 12-12 shows the maximum lin bit rates allowable to maintain this accuracy. table 12-12. maximum theoretical lin bit rates for high-speed operation 1 slic clock (mhz) max lin speed w/ 1% accuracy (bps) max lin speed w/ 1.5% accuracy (bps) 20 200,000 300,000 18 180,000 270,000 16 160,000 240,000 14 140,000 210,000 12 120,000 180,000 10 100,000 150,000 8 80,000 120,000 6 60,000 90,000 4 40,000 60,000 2 20,000 30,000
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 221 the above numbers assume a perfect input waveforms into the slcrx pin, where 1 and 0 bits are of equal length and are exactly the correct le ngth for the appropriate speed. fact ors such as physical layer wave shaping and ground shift can affect the symmetry of th ese waveforms, causing bits to appear shortened or lengthened as seen by the slic module. the user must take these f actors into account and base the maximum speed upon the shortest po ssible bit time that the slic m odule may observe, factoring in all physical layer effects. on some lin physical layer devices it is possible to turn off wave shaping circuitry for high-speed operation, removing this portion of the physical layer error. the digital receive filter can also affect high speed operati on if it is set too low and begins to filter out valid message traffic. under ideal conditions, this will not happen, as the digital filter maximum speeds allowable are higher than the speeds allowed for 1.5% accuracy. if the digital r eceive filter prescaler is set to divide-by-4; however, the fi lter delay is very close to the 1.5% accuracy maximum bit time. for example, with a slic clock of 4 mhz, the slic module is capable of maintaining 1.5% accuracy up to 60,000 bps. if the digital receive filter prescaler is set to divide-by-4, th is means that the filter will only pass message traffic which is 62,500 bps or slower under id eal circumstances. this is only a difference of 2,500 bps (4.17% of the nominal valid message traffic speed). in this case, the user must ensure that with all errors accounted for, no bi t will appear shorter than 16 s (1 bit at 62,500 bps) or the filter will block that bit. this is far too na rrow a margin for safe design practices. the better solution would be to re duce the filter prescaler, increasing the gap between the filter cut-off point and the nominal speed of valid message traffic. changing the prescaler to divide by 2 in this example gives a filter cut-off of 125,000 bps, which is 60,000 bps faster than th e nominal speed of the lin bus and much less likely to interfere with valid message traffic. to ensure that all valid messages pass the filter stage in high-speed operation, it is best to ensure that the filter cut-off point is at least 2 times the nominal speed of the fastest message traffic to appear on the bus. refer to table 12-13 for a more complete list of the digital re ceive filter delays as they relate to the maximum lin bus frequency. table 12-14 repeats much of the data found in table 12-13 ; however, the filter delay values (cutoff values) are shown in the frequency and time domains. note that table 12-14 shows the filter performance under ideal conditions. when switching between a low-sp eed (< 4800 bps) to a high-speed (> 40000 bps) lin message, the master node must allow a minimum idle time of eight bit times (of the slowes t bit rate) between the messages. this prevents a valid message at another freque ncy from being detected as an invalid message. 1 bit rates over 120,000 bits per second are not recommended for lin communications, as physical layer delay between the tx and rx pins can cause the stop bit of a byte to be mis-sampled as the last data bit. this could result in a byte framing error.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 222 freescale semiconductor table 12-13. maximum lin bit rates for high-speed operation due to digital receive filter slic clock (mhz) maximum lin bit rate for 1.5% slic accuracy (for master-slave communication (kbps) digital rx filter not considered rxfp prescaler values (see table 12-11 ) 8 (note 1) 7 (note 1) 6 (note 1) 5 (note 1) 4 (note 1) 3 (note 1) 2 1 maximum lin bit rate (kbps) 1 1 bit rates over 120,000 bits per second are not recommended for lin communications, as physical layer delay between the tx and rx pins can cause the stop bit of a byte to be mis-sampled as the last data bit. this could result in a byte framing error. 20 300 120.00 120.00 120.00 120.00 120.00 120.00 120.00 120.00 18 270 120.00 120.00 120.00 120.00 120.00 120.00 120.00 120.00 16 240 120.00 120.00 120.00 120.00 120.00 120.00 120.00 120.00 14 210 109.38 120.00 120.00 120.00 120.00 120.00 120.00 120.00 12 180 93.75 107.14 120.00 120.00 120.00 120.00 120.00 120.00 10 150 78.13 89.29 104.17 120.00 120.00 120.00 120.00 120.00 8 120 62.50 71.43 83.33 100.00 120.00 120.00 120.00 120.00 6 90 46.88 53.57 62.50 75.00 93.75 120.00 120.00 120.00 4 60 31.25 35.71 41.67 50.00 62.50 83.33 120.00 120.00 2 30 15.63 17.86 20.83 25.00 31.25 41.67 62.50 120.00 table 12-14. digital receive filter absolute cutoff (ideal conditions) 1 slic clock (mhz) max bit rate (kbps) min pulse width allowed ( s) max bit rate (kbps) min pulse width allowed ( s) max bit rate (kbps) min pulse width allowed ( s) max bit rate (kbps) min pulse width allowed ( s) rxfp = 8 rxfp = 7 rxfp = 6 rxfp = 5 20 156,250 6.40 178,571 5.60 208,333 4.80 250,000 4.00 18 140,625 7.11 160,714 6.22 187,500 5.33 225,000 4.44 16 125,000 8.00 142,857 7.00 166,667 6.00 200,000 5.00 14 109,375 9.14 125,000 8.00 145,833 6.86 175,000 5.71 12 93,750 10.67 107,143 9.33 125,000 8.00 150,000 6.67 10 78,125 12.80 89,286 11.20 104,167 9.60 125,000 8.00 8 62,500 16.00 71,429 14.00 83,333 12.00 100,000 10.00 6 46,875 21.33 53,571 18.67 62,500 16.00 75,000 13.33 4 31,250 32.00 35,714 28.00 41,667 24.00 50,000 20.00
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 223 12.6.15 bit error detection and physical layer delay the bit error detection circui try of the slic module monitors the re ceived bits to determine if they match the state of the corresponding transmitted bits. the sa mpling of the receive line takes place near the end of the bit being transmitted, so as long as the total physical layer de lay does not exceed 75% of one bit time, bit error detection will wo rk properly. for normal lin bus spee ds (<= 20 kbps), the physical layer delay in the system is typically si gnificantly lower than 75% of a bit time and bit error detection should remain enabled by the user. if the physical layer delay begins to exceed 75% of one bit time, the received bits begin to significantly lag behind the transmitted bits. in this case, it's possible for the bit error det ection circuitry to falsely sample the delayed 'previous' bit on the receive pin rather than the current b it. it is the responsibility of the user to determine if the total physi cal layer delay is large enough to requi re disabling the bit error detection circuitry. this should only be re quired at speeds higher than allowed in normal lin operations. 2 15,625 64.00 17,857 56.00 20,833 48.00 25,000 40.00 rxfp = 4 rxfp = 3 rxfp = 2 rxfp = 1 20 312,500 3.20 416,667 2.40 625,000 1.60 1,250,000 0.80 18 281,250 3.56 375,000 2.67 562,500 1.78 1,125,000 0.89 16 250,000 4.00 333,333 3.00 500,000 2.00 1,000,000 1.00 14 218,750 4.57 291,667 3.43 437,500 2.29 875,000 1.14 12 187,500 5.33 250,000 4.00 375,000 2.67 750,000 1.33 10 156,250 6.40 208,333 4.80 312,500 3.20 625,000 1.60 8 125,000 8.00 166,667 6.00 250,000 4.00 500,000 2.00 6 93,750 10.67 125,000 8.00 187,500 5.33 375,000 2.67 4 62,500 16.00 83,333 12.00 125,000 8.00 250,000 4.00 2 31,250 32.00 41,667 24.00 62,500 16.00 125,000 8.00 1 bit rates over 120,000 bits per second are not recommended for lin communications, as physical layer delay between the tx and rx pins can cause the stop bit of a byte to be mis-sample d as the last data bit. this could result in a byte framing error. table 12-14. digital receive filter absolute cutoff (ideal conditions) 1 slic clock (mhz) max bit rate (kbps) min pulse width allowed ( s) max bit rate (kbps) min pulse width allowed ( s) max bit rate (kbps) min pulse width allowed ( s) max bit rate (kbps) min pulse width allowed ( s) rxfp = 8 rxfp = 7 rxfp = 6 rxfp = 5
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 224 freescale semiconductor 12.6.16 byte transfer mode operation this subsection describes the operation and limitati ons of the optional uart- like byte transfer mode (btm). this mode allows sending and receiving individual bytes, but changes the behavior of the slcbt registers (now read/write registers) and locks the slcdlc to 1 byte data length. th e slcbt value now becomes the bit time reference for th e slic, where the software sets the length of one bit time rather than the slic module itself. this is similar to an input capture/output compare (ic/oc) count in a timer module, where the count value represents the number of slic clock counts in one bit time. byte transfer mode assumes that the user has a very stable, precise oscillator, resona tor, or clock reference input into the mcu and is therefore not appropriate for use with internal oscillators. there is no synchronization method available to th e user in this mode and the user must tell the slic how many clock counts comprise a bit time. figure 12-17 , figure 12-18 , figure 12-19 , and figure 12-20 show calculations to determine the slcbt valu e for different settings. note it is possible to use the lin autoba uding circuitry in a non-lin system to derive the correct bit timing values if system constraints allow. to do this the slic module must be activated in lin mode (btm=0) and receive a break symbol, 0x55 data byte and one additional data byte (at the desired btm speed). upon receiving this sequen ce of symbols whic h appears to be a lin header, the slic module will a ssert an id received successfully interrupt (slcsv=0x2c). the value in the slcbt registers will reflect the bit rate which the 0x55 data character was received and can be saved to ram. the user then switches the sl ic into btm mode and reloads this value from ram and the slic will be configured to communicate in btm mode at the baud rate which the 0x55 data character was sent. care must be taken to ensure that any change be tween lin and btm modes be done at known states in message traffic, such as between message frames, after an id is successfully received in lin m ode, or when the lin bus is idle as indicated by the slcact bit equal to 0. in the example in figure 12-17 , the user should write 0x16, as a writ e of 0x15 (decimal value of 21) would automatically revert to 0x14, resulting in transmitted bit times that are 1.33 slic clock periods too short rather than 0.667 slic clock periods too long. the optimal choice, which gives the smallest resolution error, is the closest even number of slic clocks to the exact calculated slcbt value. there is a trade-off between maximum bit rate and re solution with the slic in btm mode. faster slic clock speeds improve resolution, but require higher num bers to be written to the slcbt registers for a given desired bit rate. it is up to the user to determine what level of resolution is acceptable for the given application. note do not set the slcbt registers to a value lower than 16 clock counts for correct operation.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 225 figure 12-17. slcbt value calculation example 1 figure 12-18. slcbt value calculation example 2 figure 12-19. slcbt value calculation example 3 2 clock out period 42.67 slic clock periods 1 slic clock period 1 slic clock period x = 406.901 ns 1 bit 1 slic clock period = 406.901 ns 1 second 57,600 bits = 17.36111 s 1 bit 4,915,200 clock out period 1 second x 17.36111 s 1 bit desired bit rate: 57,600 bps external crystal frequency: 4.9152 mhz therefore, the closest sl cbt value would be 43 slic clocks (slcbt = 0x002b). because you can only use even values in slcbt, the closest acceptable value is 42 (0x002a). 2 clock out period 85.33 slic clock periods 1 slic clock period 1 slic clock period x = 203.45 ns 1 bit 1 slic clock period = 203.45 ns 1 second 57,600 bits = 17.36111 s 1 bit 9,830,400 clock out periods 1 second x 17.36111 s 1 bit desired bit rate: 57,600 bps external crystal frequency: 9.8304 mhz therefore, the closest sl cbt value would be 85 slic clocks (slcbt = 0x0055). because you can only use even values in slcbt, the closest acceptable value is 86 (0x0056) 2 clock out period 256 slic clock periods 1 slic clock period 1 slic clock period x = 250 ns 1 bit 1 slic clock period = 250 ns 1 second 15,625 bits = 64 s 1 bit 8,000,000 clock out periods 1 second x 64 s 1 bit desired bit rate: 15,625 bps external crystal frequency: 8.000 mhz therefore, the closest slcbt value woul d be 256 slic clocks (slcbt = 0x0100).
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 226 freescale semiconductor figure 12-20. slcbt value calculation example 4 this resolution affects the sampling accuracy of the slic module on receiving bytes, but only as far as locating the sample point of each bit within a given byte. the best sample point of the bit may be off by as much as one slic clock period from the exact center of the bit, if th e proper slcbt value for the desired bit rate is an odd number of slic clock periods. figure 12-21 shows an example of this error. in this exampl e, the user has additionally chosen an incorrect value of 30 slic clocks for the le ngth of one bit time, and a filter prescaler of 1. this makes little difference in the receive sampling of this particular bit, as the sample point is still within the bit and the digital filter will catch any noise pulses shorter than 16 filter clocks long.the ideal value of slcbt would be 35 slic clocks, but the closest available value is 34, placing the sample point at 17 slic clocks into the bit. the error in the bit time value chos en by the user in the above exampl e will grow throughout the byte, as the sample point for the next bit will be only 30 slic clock cycles later (1 full bit time at this bit rate setting). the slic resynchronizes upon every falling edge received. in a 0x00 data byte, however, there are no falling edges after th e beginning of the start bit. this mean s that the accumulated error of the sampling point over the data byte with these settings could be as high as 30 slic clock cycles (10 bits x {2 slic clocks due to user error + 1 slic clock resolution error}) pl acing it at the bounda ry between the last bit and the stop bit. this could result in miss ampling and missing a byte framing error on the last bit on high speed communications when the slcbt count is relatively low. a properly chosen slcbt value would result in a maximum error of 10 slic clock counts over a given byte. this is less than one filter delay time, and will not cause missampli ng of any of the bits in that byte. at the falling edge of the next start bit, the slic will resynchronize and any accumulated sampling error returns to 0. the sampling error becomes even less significant at lowe r speeds, when higher valu es of slcbt are used to define a bit time, as the worst case bit time resolution error is stil l only one slic clock per bit (or maximum of 10 slic clocks per byte). 2 clock out period 416.017 slic clock periods 1 slic clock period 1 slic clock period x = 250 ns 1 bit 1 slic clock period = 250 ns 1 second 9,615 bits = 104.004 s 1 bit 8,000,000 clock out periods 1 second x 104.004 s 1 bit desired bit rate: 9,615 bps external crystal frequency: 8.000 mhz therefore, the closest slcbt value woul d be 416 slic clocks (slcbt = 0x01a0).
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 227 figure 12-21. btm mode receive byte sampling example the error also comes into effect with transmitted bit times. using the previous example with a slcbt value of 34, transmitted bits will appear as 34 slic clock periods long. this is one slic clock short of the proper length. depending on the fre quency of the slic clock, one peri od of the slic clock might be a large or a small fraction of one id eal bit time. raising the frequency of the slic clock will reduce this error relative to the ideal bit time, improving the resolution of the slic clock relative to the bit rate of the bus. in any case, the error is still one slic clock cycle. raising the slic clock frequency, however, requires programming a higher va lue for slcbt to maintain the same target bit rate. smaller values of slcbt combined with higher values of the slic cl ock frequency (smaller clock period) will give faster bit rates, but the slic clock peri od becomes an increasingly si gnificant portion of one bit time. because btm mode does not perform any synchronizati on and relies on the accurac y of the data provided by the user software to set its sample point and ge nerate transmitted bits, the constraint on maximum speeds is only limited to the limits imposed by the di gital filter delay and the slic input clock. because the digital filter delay cannot be less than 16 slic clock cycles, the fastest possible pulse which would pass the filter is 16 clock pe riods at 8 mhz, or 500,000 bits/second. the values shown in table 12-14 are the same values shown in table 12-15 and indicate the absolute fastest bit rates which could just pass the minimum digital filter settings (prescaler = divide by 1) under perfect conditions. filtered rx data filter clock unfiltered rx data 16 filter clocks (31 prescale) filter begins filter reaches 0x0 filter begins filter reaches 0xf and toggles filter output and toggles filter output slic clock (31 prescale) 15 slic clocks counting up 35 slic clocks counting down slic sample point (based on slcbt value) this example assumes a slcbt value of 30 (0x1e). ideal slic sample point (17 slic clocks) transmitted bits will be sent out as 30 slic clock cycles long. the proper closest slcbt setting would be 34 (0x22), which gives the ideal sample point of 17 slic clocks and transmitted bits are 34 slic clocks long. (31 prescale) 16 filter clocks (31 prescale) (1/2 of slcbt value) (actual filtered bit length)
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 228 freescale semiconductor because perfect conditions are almost impossible to attain, more robust values must be chosen for bit rates. for reliable communication, it is best to ensure that a bit time is no smalle r 2x?3x longer than the filter delay on the digital receive fi lter. this is true in lin or btm mode and ensures that valid data bits which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by the filter without exception. this would translate to 2x to 3x reduction in the maximum speeds shown in table 12-14 . recommended maximum bit rates are shown in table 12-15 , and ensure that a single bit time is at least twice the length of one filt er delay value. if system noise is not adequately filtered out it might be necessary to change the prescaler of the filter and lower the bit rate of the communication. if valid communications are bei ng absorbed by the filter, corrective action mu st be taken to ensure that either the bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset, asymmetrical rise/f all times, insufficient physic al layer supply voltage, etc.). 12.6.17 oscillator trimming with slic slcact can be used as an indicator of lin bus activity. slcact tells the user that the slic is currently processing a message header (therefore synchroni zing to the bus) or proc essing a message frame (including checksum). theref ore, at idle times betwee n message frames or duri ng a message frame which has been marked as a ?don?t care? by writing imsg, it is possi ble to trim the oscillat or circuit of the mcu with no impact to the lin communications. it is important to note the exact mechanisms with which the slic sets and cl ears slcact. any falling edge which successfully passes through the digital receive filter will cau se slcact to become set. this might even include noise pulses, if they are of suff icient length to pass throu gh the digital rx filter. although in these cases slcact is becoming set on a noise spike, it is very proba ble that noise of this nature will cause othe r system issues as well such as corrupti on of the message frame. the software can then further qualify if it is a ppropriate to trim the oscillator. table 12-15. recommended maximum bit rates for btm operation due to digital filter slic clock (mhz) maximum btm bit rate (kbps) rxfp = 8 rxfp = 7 rxfp = 6 rxfp = 5 rxfp = 4 rxfp = 3rxfp = 2rxfp = 1 20 78.125 89.286 104.167 120.000 120.000 120.000 120.000 120.000 18 70.313 80.357 93.750 112.500 120.000 120.000 120.000 120.000 16 62.500 71.429 83.333 100.000 120.000 120.000 120.000 120.000 14 54.688 62.500 72.917 87.500 109.375 120.000 120.000 120.000 12 46.875 53.571 62.500 75.000 93.750 120.000 120.000 120.000 10 39.063 44.643 52.083 62.500 78.125 104.167 120.000 120.000 8 31.250 35.714 41.667 50.000 62.500 83.333 120.000 120.000 6 23.438 26.786 31.250 37.500 46.875 62.500 93.750 120.000 4 15.625 17.857 20.833 25.000 31.250 41.667 62.500 120.000 2 7.813 8.929 10.417 12.500 15.625 20.833 31.250 62.500
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 229 slcact will only be cleared by the slic upon successful completion of a normal lin message frame (see section , ? ,? description for more detail). this means that in some cases, if a message frame terminates with an error condition or some source other than those cited in the slcact bit description, slcact might remain set during an otherwise idle bus ti me. slcact will then clear upon the successful completion of the next lin message frame. these mechanisms might result in sl cact being set when it is safe (f rom the slic modul e perspective) to trim the oscillator. however, slca ct will only be clear when the sl ic considers it safe to trim the oscillator. in a particular system, it might also be possible to improve the opportunities for trimm ing by using system knowledge and use of imsg. if a messa ge id is known to be considered a ?don?t care? by this particular node, it should be safe to trim the oscillator during th at message frame (provided that it is safe for the application software as we ll). after the software has done an identifier lookup and determined that the id corresponds to a ?don?t care? messag e, the software might choose to set imsg. from that time, the application software should have at least one byte time of message traffi c in which to trim the oscillator before that ignored message frame expires, regardless of the state of slcact. if the length of that ignored message frame is known, that knowledge might also be used to extend the time of this os cillator trimming opportunity. now that the mechanisms for recognizing when th e slic module indicates sa fe oscillator trimming opportunities are understood, it is im portant to understand ho w to derive the information needed to perform the trimming. the value in slcbt will indicate how many slic clock cycles comprise one bit time and for any given lin bus speed, this will be a fixed value if the oscillator is running at it s ideal frequency. it is possible to use this ideal value combined with the measured value in slcbt to determine how to adjust the oscillator of the microcontroller. the actual oscillator trimming algorithm is very specific to each partic ular implementation, and applications might or might not require the oscillator even to be trimmed. the slic can maintain communications even with i nput oscillator variation of 50% (with 4 mhz nomin al, that means that any input clock into the slic from 2 mhz to 6 mhz will still guarantee communications ). because freescale internal oscillators are at least within 25% of their nominal value, even when untrimmed, this means that trimming of the oscillator is not even required for lin communications. if the application can tolerate the range of frequencies which might appear within this ma nufacturing range, then it is not necessary ever to trim the oscillator. this can be a tremendous advantage to the customer, enabling migration to very low-cost rom devices which ha ve no non-volatile memory in which to store the trim value. note even though most internal oscillators are within 25% before trimming, they are stable at some frequency in that range, within at least 5% over the entire operating voltage and temper ature range. the trimming operation simply eliminates the offset due to factory manufacturing variations to re-center the base oscillat or frequency to the nominal value. please re fer to the electrical specifications for the oscillator for more specific information, as exact specificati ons might differ from module to module.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 230 freescale semiconductor 12.6.18 digital receive filter the receiver section of the slic module includes a digital low-pass filter to rem ove narrow noise pulses from the incoming message. a block diagra m of the digital filter is shown in figure 12-22 . figure 12-22. slic module rx digital filter block diagram 12.6.18.1 digital f ilter operation the clock for the digital filter is provided by the slic interface clock. at each positive e dge of the clock signal, the current state of the receiver input signa l from the slcrx pad is sampled. the slcrx signal state is used to determine whether the counter should incremen t or decrement at the next positive edge of the clock signal. the counter will increment if the i nput data sample is high but decrement if the input sample is low. the counter will thus progress up towa rds the highest count value (deter mined by rxfp bit settings), on average, the slcrx signal remains high or progress down towards ?0? if, on average, the slcrx signal remains low. the final counter value which determines when the filter will cha nge state is generated by shifting the rxfp value right three positions and bi twise or-ing the result with the value 0x0f. for example, a prescale setti ng of divide by 3 would give a count value of 0x2f. when the counter eventually reaches this value, the digital filter decides that the condition of the slcrx signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the c ounter is prevented from overflowing and can only be decremented from this state. alternatively, when the counter eventu ally reaches the value ?0?, the dig ital filter decides that the condition of the slcrx signal is at a stable logi c level 0 and the data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, the counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the c ounter next reaches the oppos ite end point, signifying a definite transition of the slcrx signal. dq up/down out 4 edge & count comparator dq filtered rx data out slic clock rx data from slcrx pin input sync 4-bit up/down counter digital rx filter prescaler (rxfp) hold
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 231 12.6.18.2 digital filter performance the performance of the digital filter is best described in the time dom ain rather than the frequency domain. if the signal on the slcrx signal transitions, then there will be a delay before th at transition appears at the filtered rx data output signal. this delay will be between 15 a nd 16 clock periods, depending on where the transition occurs with respect to the sampling point s. this ?filter delay? is not an issue for slic operation, as there is no need for message arbitration. the effect of random noise on the slcrx signal depends on the characteristics of the noise itself. narrow noise pulses on the slcrx signal will be completely ignored if they are s horter than the filter delay. this provides a degree of low-pass filtering. figure 12-22 shows the configuration of the digital receive filter and the consequential effect on the filter delay. th is filter delay valu e indicates that for a particular setup, only pulses of which are greater than the filter delay will pass the filter. for example, if the frequency of the slic clock (f slic ) is 3.2 mhz, then the period (t slic ) is of the slic clock is 313 ns. with a r eceive filter prescaler setti ng of division by 3, the resu lting maximum filter delay in the absence of noise will be 15.00 s. by simply changing the prescaler of the receive filter, the user can then select alternatively 5 s, 10 s, or 20 s as a minimum filter delay according to the systems requirements. if noise occurs during a symbol transition, the detection of that tr ansition may be delayed by an amount equal to the length of the noise burst. this is just a reflection of the unc ertainty of where the transition is truly occurring within the noise. note the user must always account for the worst case bit timi ng of their lin bus when configuring the digital receive fi lter, especially if running at faster speeds. ground offset and other physical layer conditions can cause shortening of bits as seen at the digi tal receive pin, for example. if these shortened bit lengths are less than the filt er delay, the bits will be interpreted by the filter as noise and will be bl ocked, even though the nominal bit timing might be greater than the filter delay.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 232 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 233 chapter 13 serial peripheral interface (s08spiv3) 13.1 introduction the serial peripheral interface (spi) module provides full-duple x, synchronous, serial communication between the mcu and peripheral devices. these peri pheral devices can include other microcontrollers, analog-to-digital converters, shift regist ers, sensors, memories, and so forth. the maximum spi baud rate de pends on the operating mode: ? master mode ? bus clock divided by two ? slave mode ? bus clock divided by four the spi operation can be driven by interrupt s or software can poll the status flags. all devices in the mc9s08el32 series and mc 9s08sl16 series mcus contain one spi module figure 13-1 highlights the spi module.
chapter 13 serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 234 freescale semiconductor figure 13-1. mc9s08el32 block diagra m highlighting spi block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 235 13.1.1 features features of the spi module include: ? master or slave mode operation ? full-duplex or single-w ire bidirectional option ? programmable transmit bit rate ? double-buffered transmit and receive ? serial clock phase and polarity options ? slave select output ? selectable msb-first or lsb-first shifting 13.1.2 block diagrams this section includes block diagrams showing spi system c onnections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate. 13.1.2.1 spi system block diagram figure 13-2 shows the spi modules of two mcus connected in a master-slave arrangement. the master device initiates all spi data transfers. during a transfer, the master sh ifts data out (on th e mosi pin) to the slave while simultaneously shifting data in (on the miso pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input (ss pin). in this system, the mast er device has c onfigured its ss pin as an optional slave select output. figure 13-2. spi system connections 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter ss spsck miso mosi ss spsck miso mosi master slave
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 236 freescale semiconductor the most common uses of the spi system include c onnecting simple shift regi sters for adding input or output ports or connecting small pe ripheral devices such as serial a/d or d/a converters. although figure 13-2 shows a system where data is exchanged between two mcus, many practical systems involve simpler connections where data is unidirectionally transfer red from the master mcu to a slave or from a slave to the master mcu. 13.1.2.2 spi module block diagram figure 13-3 is a block diagram of the spi module. the central element of th e spi is the spi shift register. data is written to the d ouble-buffered transmitter (write to spid) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from spid). pi n multiplexing logic controls connections between mcu pins and the spi module. when the spi is configured as a master, the clock out put is routed to the spsc k pin, the shifter output is routed to mosi, and the shifter input is routed from the miso pin. when the spi is configured as a slave, the spsck pin is routed to the clock i nput of the spi, the shifter output is routed to miso, and the shifte r input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly different names for these pins.
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 237 figure 13-3. spi module block diagram 13.1.3 spi baud rate generation as shown in figure 13-4 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) di vide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie modfen ssoe spc0 bidiroe spibr tx buffer (write spid) rx buffer (read spid)
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 238 freescale semiconductor figure 13-4. spi baud rate generation 13.2 external signal description the spi optionally shares four port pi ns. the function of these pins depe nds on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins re vert to being general-pur pose port i/o pins that are not controlled by the spi. 13.2.1 spsck ? spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. wh en the spi is enabled as a master, this pin is the serial clock output. 13.2.2 mosi ? master data out, slave data in when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc 0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master m ode is selected, this pin becomes the bidirectional data i/o pin (mom i). also, the bidirecti onal mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a gene ral-purpose port i/o pin. 13.2.3 miso ? master da ta in, slave data out when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enable d as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is se lected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bid iroe = 1). if spc0 = 1 and ma ster mode is selected, this pin is not used by the spi and reve rts to being a general-purpose port i/o pin. 13.2.4 ss ? slave select when the spi is enabled as a slave, this pin is the lo w-true slave select input. wh en the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not us ed by the spi and reverts to being a general-purpose port i/o pin. when the spi is enabled as a master and modf en = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler clock rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 239 13.3 modes of operation 13.3.1 spi in stop modes the spi is disabled in all stop mode s, regardless of the settings befo re executing the stop instruction. during either stop1 or stop2 mode, th e spi module will be fully powered down. upon wake-up from stop1 or stop2 mode, the spi module will be in the reset st ate. during stop3 mode, cloc ks to the spi module are halted. no registers are affected. if st op3 is exited with a reset, the spi wi ll be put into its reset state. if stop3 is exited with an interrupt, the spi continues from the state it was in when stop3 was entered. 13.4 register definition the spi has five 8-bit registers to select spi options, control ba ud rate, report spi status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all spi registers. this section refers to register s and control bits only by their names, and a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.4.1 spi control register 1 (spic1) this read/write register includes the spi enable control, interrupt enables, and configuration options. 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w r e s e t00000100 figure 13-5. spi control register 1 (spic1) table 13-1. spic1 field descriptions field description 7 spie spi interrupt enable (for sprf and modf) ? this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 0 interrupts from sprf and modf inhibited (use polling) 1 when sprf or modf is 1, request a hardware interrupt 6 spe spi system enable ? disabling the spi halts any trans fer that is in progress, clears data buffers, and initializes internal state machines. sprf is cleared and sptef is set to indicate the spi transmit data buffer is empty. 0 spi system inactive 1 spi system enabled 5 sptie spi transmit interrupt enable ? this is the interrupt enable bit for spi transmit buffer empty (sptef). 0 interrupts from sptef inhibited (use polling) 1 when sptef is 1, hardware interrupt requested
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 240 freescale semiconductor note ensure that the spi should not be disa bled (spe=0) at the same time as a bit change to the cpha bit. these changes should be performed as separate operations or unexpected behavior may occur. 13.4.2 spi control register 2 (spic2) this read/write register is used to control optional featur es of the spi system. bits 7, 6, 5, and 2 are not implemented and always read 0. 4 mstr master/slave mode select 0 spi module configured as a slave spi device 1 spi module configured as a master spi device 3 cpol clock polarity ? this bit effectively places an inverter in series with the clock signal from a master spi or to a slave spi device. refer to section 13.5.1, ?spi clock formats ? for more details. 0 active-high spi clock (idles low) 1 active-low spi clock (idles high) 2 cpha clock phase ? this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to section 13.5.1, ?spi clock formats ? for more details. 0 first edge on spsck occurs at the middle of the first cycle of an 8-cycle data transfer 1 first edge on spsck occurs at the start of the first cycle of an 8-cycle data transfer 1 ssoe slave select output enable ? this bit is used in combination with the mode fault enable (modfen) bit in spcr2 and the master/slave (mstr) contro l bit to determine the function of the ss pin as shown in table 13-2 . 0 lsbfe lsb first (shifter direction) 0 spi serial data transfers start with most significant bit 1 spi serial data transfers start with least significant bit table 13-2. ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10s s input for mode fault slave select input 1 1 automatic ss output slave select input 76543210 r000 modfen bidiroe 0 spiswai spc0 w r e s e t00000000 = unimplemented or reserved figure 13-6. spi control register 2 (spic2) table 13-1. spic1 field descriptions (continued) field description
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 241 13.4.3 spi baud rate register (spibr) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. table 13-3. spic2 register field descriptions field description 4 modfen master mode-fault function enable ? when the spi is configured for sl ave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in mast er mode, this bit determines how the ss pin is used (refer to ta b l e 1 3 - 2 for more details). 0 mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi 1 mode fault function enabled, master ss pin acts as the mode fault input or the slave select output 3 bidiroe bidirectional mode output enable ? when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is configured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/ o pin. when spc0 = 0, bidiroe has no meaning or effect. 0 output driver disabled so spi data i/o pin acts as an input 1 spi i/o pin enabled as an output 1 spiswai spi stop in wait mode 0 spi clocks continue to operate in wait mode 1 spi clocks stop when the mcu enters wait mode 0 spc0 spi pin control 0 ? the spc0 bit chooses single-wire bidirectional mode. if mstr = 0 (slave mode), the spi uses the miso (siso) pin for bidirectional spi data tr ansfers. if mstr = 1 (master mode), the spi uses the mosi (momi) pin for bidirectional spi data transfers. when spc0 = 1, bidiroe is used to enable or disable the output driver for the single bidirectional spi i/o pin. 0 spi uses separate pins for data input and data output 1 spi configured for single-wire bidirectional operation 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w r e s e t00000000 = unimplemented or reserved figure 13-7. spi baud rate register (spibr) table 13-4. spibr register field descriptions field description 6:4 sppr[2:0] spi baud rate prescale divisor ? this 3-bit field selects one of eight divisors for the spi baud rate prescaler as shown in ta b l e 1 3 - 5 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 13-4 ). 2:0 spr[2:0] spi baud rate divisor ? this 3-bit field selects one of eight diviso rs for the spi baud rate divider as shown in ta b l e 1 3 - 6 . the input to this divider comes from the spi baud rate prescaler (see figure 13-4 ). the output of this divider is the spi bit rate clock for master mode.
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 242 freescale semiconductor 13.4.4 spi status register (spis) this register has three read-only st atus bits. bits 6, 3, 2, 1, and 0 are not implemented and always read 0. writes have no meaning or effect. table 13-5. spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 table 13-6. spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 76543210 r sprf 0 sptef modf 0 0 0 0 w r e s e t00100000 = unimplemented or reserved figure 13-8. spi status register (spis)
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 243 13.4.5 spi data register (spid) reads of this register return the data read from the rece ive data buffer. writes to th is register write data to the transmit data buffer. when the spi is configured as a master, writi ng data to the transmit data buffer initiates an spi transfer. data should not be written to the transmit data buf fer unless the spi transmit buffer empty flag (sptef) is set, indicating there is room in the transmit buffer to queue a new transmit byte. data may be read from spid any time after sprf is set and before anothe r transfer is fini shed. failure to read the data out of the receive data buffer before a new transfer ends causes a recei ve overrun condition and the data from the new transfer is lost. table 13-7. spis register field descriptions field description 7 sprf spi read buffer full flag ? sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spid). sprf is clea red by reading sprf while it is set, then reading the spi data register. 0 no data available in the receive data buffer 1 data available in the receive data buffer 5 sptef spi transmit buffer empty flag ? this bit is set when there is room in the transmit data buffer. it is cleared by reading spis with sptef set, followed by writing a data value to the transmit buffer at spid. spis must be read with sptef = 1 before writing data to spid or the spid write will be ignored. sptef generates an sptef cpu interrupt request if the sptie bit in the spic1 is also set. sptef is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. fo r an idle spi (no data in th e transmit buffer or the shift register and no transfer in progress), data written to spid is transferred to the shifter almost immediately so sptef is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. after completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and sptef will be set to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer , sptef simply remains set and no data moves from the buffer to the shifter. 0 spi transmit buffer not empty 1 spi transmit buffer empty 4 modf master mode fault flag ? modf is set if the spi is configured as a master and the slave select input goes low, indicating some other spi device is also configured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spic1). 0 no mode fault error 1 mode fault error detected 76543210 r bit 7654321bit 0 w reset00000000 figure 13-9. spi data register (spid)
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 244 freescale semiconductor 13.5 functional description an spi transfer is initiated by checking for the spi transmit buffer empty flag (sptef = 1) and then writing a byte of data to the spi data register (spid) in the master spi device. when the spi shift register is available, this byte of data is m oved from the transmit data buffer to th e shifter, sptef is set to indicate there is room in the buffer to queue another transmit character if desired, and the spi serial transfer starts. during the spi transfer, data is sampled (read) on th e miso pin at one spsck e dge and shifted, changing the bit value on the mosi pin, one-half spsck cycle la ter. after eight spsck cycles, the data that was in the shift register of the master has been shifted out the mosi pin to the slave while eight bits of data were shifted in the miso pin into the master?s shift re gister. at the end of this transfer, the received data byte is moved from the shifter into th e receive data buffer and sprf is set to indicate the da ta can be read by reading spid. if another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, sptef is set, and a new transfer is started. normally, spi data is transferred most significant bit (msb) first. if th e least significant bit first enable (lsbfe) bit is set, spi data is shifted lsb first. when the spi is configur ed as a slave, its ss pin must be driven low befo re a transfer starts and ss must stay low throughout the tran sfer. if a clock format wh ere cpha = 0 is selected, ss must be driven to a logic 1 between successive transfers. if cpha = 1, ss may remain low between successive transfers. see section 13.5.1, ?spi clock formats ? for more details. because the transmitter a nd receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffe r, and a previously rece ived character can be in the receive data buffer while a new character is being shifted in. the sptef flag indicates when the transmit buffer has room for a new character. the sprf flag indicates when a received character is available in the receive data buffer. the received char acter must be read out of the receive buffer (read spid) before the next transfer is fini shed or a receive overrun error results. in the case of a receive overrun, the new data is lo st because the receive buffer still held the previous character and was not ready to accept the new data. there is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 13.5.1 spi clock formats to accommodate a wide variety of synchronous serial peripherals from differen t manufacturers, the spi system has a clock polarity (cpol) bi t and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol se lectively inserts an inverter in series with the clock. cpha chooses between two different clock phase rela tionships between the clock and data. figure 13-10 shows the clock formats when cpha = 1. at th e top of the figure, th e eight bit times are shown for reference with bit 1 st arting at the first spsck edge and bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb first and ls b first lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are show n, but only one of these waveforms applies for a specific transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slav e or the miso input of a master. the mosi waveform applies to the
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 245 mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output fr om a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle before the start of the transfer and goes back high at the end of the eighth bi t time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 13-10. spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not defined until the first spsck edge. the first spsck edge shifts the first bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi input s, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when chpa = 1, the slave?s ss input is not required to go to its inactive high level between transfers. figure 13-11 shows the clock formats when cpha = 0. at th e top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (ss in goes low), and bit 8 ends at the last spsck edge. the msb first and lsb fi rst lines show the order of spi data bits dependi ng on the setting bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 246 freescale semiconductor in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the va lue in cpol. the sample in wave form applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso wavefo rm applies to the miso out put from a slave. the ss out waveform applies to the slave select output fr om a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the fi rst bit time of the transfer and goe s back high one-half spsck cycle after the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 13-11. spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the first data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the first spsck edge causes both the master and the slave to sample the data bit valu es on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was ju st sampled and shifts the second data bit value out the other end of the shifte r to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slave?s ss input must go to its in active high level between transfers. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 247 13.5.2 spi interrupts there are three flag bits, two interr upt mask bits, and one interrupt vect or associated with the spi system. the spi interrupt enable mask (spie) enables interrupt s from the spi receiver full flag (sprf) and mode fault flag (modf). the spi transm it interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty fl ag (sptef). when one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated flag bits instead of using inte rrupts. the spi interrupt se rvice routine (isr) should check the flag bits to de termine what event caused the interrupt. the service routine should also clear the flag bit(s) before returning from the is r (usually near the beginning of the isr). 13.5.3 mode fault detection a mode fault occurs and th e mode fault flag (modf) becomes set wh en a master spi device detects an error on the ss pin (provided the ss pin is configured as the m ode fault input signal). the ss pin is configured to be the mode fault input signal when mstr = 1, mode fault enable is set (modfen = 1), and slave select output enable is clear (ssoe = 0). the mode fault detection f eature can be used in a system where mo re than one spi de vice might become a master at the same t ime. the error is detect ed when a master?s ss pin is low, indicating that some other spi device is trying to addre ss this master as if it were a slave. th is could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all spi output driver s when such an error is detected. when a mode fault is detected, modf is set and mstr is cleared to change the spi configuration back to slave mode. the output drivers on the spsck, mo si, and miso (if not bi directional mode) are disabled. modf is cleared by reading it while it is set, then writing to the spi control register 1 (spic1). user software should verify the error condition has been corrected before changing the spi back to master mode.
serial peripheral interface (s08spiv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 248 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 249 chapter 14 serial communications interface (s08sciv4) 14.1 introduction the mc9s08el32 series and mc9s08sl16 series incl ude a specially designed serial communications interface modules. note the mc9s08el32 series and mc9s08sl16 series family of devices operates at a higher voltage range (2.7 v to 5.5 v) and does not include stop1 mode.
chapter 14 serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 250 freescale semiconductor figure 14-1. mc9s08el32 series and mc9s08sl16 series block diagram highlighting sci block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 251 14.1.1 features features of sci module include: ? full-duplex, standard non-re turn-to-zero (nrz) format ? double-buffered transmitter and re ceiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing erro r, and noise error ? idle receiver detect ? active edge on receive pin ? break detect supporting lin ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver wakeup by idle-line or address-mark ? optional 13-bit break character generati on / 11-bit break character detection ? selectable transmitt er output polarity 14.1.2 modes of operation see section 14.3, ?functio nal description ,? for details concerning sci operation in these modes: ? 8- and 9-bit data modes ? stop mode operation ? loop mode ? single-wire mode
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 252 freescale semiconductor 14.1.3 block diagram figure 14-2 shows the transmitter portion of the sci. figure 14-2. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd txinv brk13
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 253 figure 14-3 shows the receiver portion of the sci. figure 14-3. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rxinv lbkde rwuid
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 254 freescale semiconductor 14.2 register definition the sci has eight 8-bit registers to control baud ra te, select sci options, report sci status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.2.1 sci baud rate regi sters (scixbdh, scixbdl) this pair of registers co ntrols the prescale diviso r for sci baud rate genera tion. to update the 13-bit baud rate setting [sbr12:sbr0], first writ e to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate genera tor remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scixc2 are written to 1). 76543210 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w r e s e t00000000 = unimplemented or reserved figure 14-4. sci baud rate register (scixbdh) table 14-1. scixbdh field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif flag is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif flag is 1. 4:0 sbr[12:8] baud rate modulo divisor ? the 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 4 - 2 .
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 255 14.2.2 sci control register 1 (scixc1) this read/write register is used to contro l various optional features of the sci system. 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset00000100 figure 14-5. sci baud rate register (scixbdl) table 14-2. scixbdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ? these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 4 - 1 . 76543210 r loops sciswai rsrc m wake ilt pe pt w r e s e t00000000 figure 14-6. sci control register 1 (scixc1) table 14-3. scixc1 field descriptions field description 7 loops loop mode select ? selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ? rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter output s are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 6 sciswai sci stops in wait mode 0 sci clocks continue to run in wait mode so the sci c an be the source of an interrupt that wakes up the cpu. 1 sci clocks freeze while cpu is in wait mode. 5 rsrc receiver source select ? this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connecte d to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ? start + 8 data bits (lsb first) + stop. 1 receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 256 freescale semiconductor 14.2.3 sci control register 2 (scixc2) this register can be read or written at any time. 3 wake receiver wakeup method select ? refer to section 14.3.3.2, ?recei ver wakeup operation ? for more information. 0 idle-line wakeup. 1 address-mark wakeup. 2 ilt idle line type select ? setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. refer to section 14.3.3.2.1, ?idle-line wakeup ? for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable ? enables hardware parity generation and checking. when parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treat ed as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type ? provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bi t, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 0 even parity. 1 odd parity. 76543210 r tie tcie rie ilie te re rwu sbk w reset00000000 figure 14-7. sci control register 2 (scixc2) table 14-4. scixc2 field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre flag is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc flag is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf flag is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle flag is 1. table 14-3. scixc1 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 257 14.2.4 sci status register 1 (scixs1) this register has eight read-only st atus flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 14.3.2.1, ?send break and queued idle ? for more details. when te is written to 0, the transmitt er keeps control of the port txd pi n until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ? when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on. 1 rwu receiver wakeup control ? this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 14.3.3.2, ?rec eiver wakeup operation ? for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wakeup condition. 0 sbk send break ? writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relati ve to the information currently being transmitted, a second break character may be queued before software clears sbk. refer to section 14.3.2.1, ?send break and queued idle ? for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. 76543210 r tdre tc rdrf idle or nf fe pf w r e s e t11000000 = unimplemented or reserved figure 14-8. sci status register 1 (scixs1) table 14-4. scixc2 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 258 freescale semiconductor table 14-5. scixs1 field descriptions field description 7 tdre transmit data register empty flag ? tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving r oom for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ? tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmi ssion activity complete). tc is cleared automatically by read ing scixs1 with tc = 1 and then doing one of the following three things: ? write to the sci data register (scixd) to transmit new data ? queue a preamble by changing te from 0 to 1 ? queue a break character by writing 1 to sbk in scixc2 5 rdrf receive data register full flag ? rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ? idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn?t start counting idle bit times until after the stop bit. so th e stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag ? or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost bec ause there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag ? the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if an y of these samples disagrees with the rest of the samples within any bit time in the frame, the flag nf will be set at the same time as the flag rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 0 no noise detected. 1 noise detected in the received character in scixd.
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 259 14.2.5 sci status register 2 (scixs2) this register has one read-only status flag. 1 fe framing error flag ? fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ? pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 0 no parity error. 1 parity error. 76543210 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf w r e s e t00000000 = unimplemented or reserved figure 14-9. sci status register 2 (scixs2) table 14-6. scixs2 field descriptions field description 7 lbkdif lin break detect interrupt flag ? lbkdif is set when the lin break detect circuitry is enabled and a lin break character is detected. lbkdif is cleared by writing a ?1? to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ? rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ?1? to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv 1 receive data inversion ? setting this bit reverses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect ? rwuid controls whether the idle charac ter that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length ? brk13 is used to select a longer transmitted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is transmitted with length of 10 bit times (11 if m = 1) 1 break character is transmitted with length of 13 bit times (14 if m = 1) table 14-5. scixs1 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 260 freescale semiconductor when using an internal oscillator in a lin system, it is necessary to raise the break detection threshold by one bit time. under the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slav e which is running 14% faster than the master. this would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing errors are inhibited and the break detectio n threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 14.2.6 sci control register 3 (scixc3) 1 lbkde lin break detection enable ? lbkde is used to select a longer break character detection length. while lbkde is set, framing error (fe) and receive data regi ster full (rdrf) flags are prevented from setting. 0 break character is detected at length of 10 bit times (11 if m = 1). 1 break character is detected at length of 11 bit times (12 if m = 1). 0 raf receiver active flag ? raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status flag can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). 1 setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. 76543210 rr8 t8 txdir txinv orie neie feie peie w r e s e t00000000 = unimplemented or reserved figure 14-10. sci control register 3 (scixc3) table 14-7. scixc3 field descriptions field description 7 r8 ninth data bit for receiver ? when the sci is configured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered da ta in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd complete s automatic flag clearing sequences which could allow r8 and scixd to be overwritten with new data. 6 t8 ninth data bit for transmitter ? when the sci is configured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd regi ster. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after scixd is written so t8 should be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. 5 txdir txd pin direction in single-wire mode ? when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines t he direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. table 14-6. scixs2 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 261 14.2.7 sci data register (scixd) this register is actually two separate registers. r eads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and wr ites of this register are also involved in the automatic flag clearing mechanisms for the sci status flags. 14.3 functional description the sci allows full-duplex, as ynchronous, nrz serial communica tion among the mcu and remote devices, including other mcus. the sc i comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver opera te independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following desc ribes each of the blocks of the sci. 14.3.1 baud rate generation as shown in figure 14-12 , the clock source for the sci baud rate generator is the bus-rate clock. 4 txinv 1 transmit data inversion ? setting this bit reverses the pola rity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted 3 orie overrun interrupt enable ? this bit enables the overrun flag (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ? this bit enables the noise flag (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ? this bit enables the framing error flag (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ? this bit enables the parity error flag (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. 1 setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. 76543210 rr 7r 6r 5r 4r 3r 2r 1r 0 wt 7t 6t 5t 4t 3t 2t 1t 0 r e s e t00000000 figure 14-11. sci data register (scixd) table 14-7. scixc3 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 262 freescale semiconductor figure 14-12. sci baud rate generation sci communications require the transmitter and re ceiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolera nce on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundari es on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5 percent for 8-bit data format and about 4 percent for 9-bit data format. alt hough baud rate modulo divider settings do not always produce baud rates that exactly match st andard rates, it is normally possi ble to get within a few percent, which is acceptable for reliable communications. 14.3.2 transmitter functional description this section describes the overall block diagram for th e sci transmitter, as well as specialized functions for sending break and idle characters. the transmitter block diagram is shown in figure 14-2 . the transmitter output (txd) idle state defaults to logic high (txinv = 0 following reset). the transmitter output is inverted by setting txinv = 1. the transmitter is enabled by se tting the te bit in scixc2. this queues a preamble character that is one full character fr ame of the idle state. th e transmitter then remains idle until data is available in the tr ansmit data buffer. progr ams store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmit ter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the m control bit. for th e remainder of this section, we will assume m = 0, selecting the normal 8-bi t data mode. in 8-bit data m ode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmit data register is transfer red to the shift register (synchronized with the ba ud rate clock) and the transmit data register empt y (tdre) status flag is set to indicate another character may be written to the transmit data buffer at scixd. if no new character is waiting in th e transmit data buffer after a stop bit is shifted out the txd pin, the transmitter sets the transmit comp lete flag and enters an idle m ode, with txd high, waiting for more characters to transmit. sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 263 writing 0 to te does not immediately release the pin to be a general-pur pose i/o pin. any tr ansmit activity that is in progress must first be completed. this includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer break of 13 bit times can be enabled by setting brk13 = 1. normally, a program would wait for tdre to become se t to indicate the last ch aracter of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is avai lable. if sbk is st ill 1 when the queue d break moves into the shifter (synchronized to the baud ra te clock), an additional break char acter is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifte r, then write 0 and then write 1 to the te bit. this action queues an idle ch aracter to be sent as soon as the shifter is available. as long as the character in the shifter does not finish while te = 0, th e sci transmitter never actually re leases control of the txd pin. if there is a possibility of the shifter finishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affected by the brk13 and m bits as shown below. 14.3.3 receiver functional description in this section, the r eceiver block diagram ( figure 14-3 ) is used as a guide for the overall receiver functional description. next, the data sampling technique used to reconstruc t receiver data is described in more detail. finally, two variations of the receiver wakeup function are explained. the receiver input is inverted by setting rxinv = 1. the receiver is enabled by setting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine ) data bits (lsb first), and a stop bit of logic 1. for information ab out 9-bit data mode, refer to section 14.3.5.1, ?8- and 9-bit data modes .? for the remainder of this discussion, we assume the sci is confi gured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive da ta register and the receive data register full (rdrf) table 14-8. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 264 freescale semiconductor status flag is set. if rdrf was already se t indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. because the sci re ceiver is double-buffered, the program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user?s program that handles receive data. refer to section 14.3.4, ?interrupts and status flags ? for more details about flag clearing. 14.3.3.1 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiv er starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is defined as a logic 0 sample after thre e consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a fa lling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure this was a real start bit a nd not merely noise. if at least two of these three samples ar e 0, the receiver assumes it is s ynchronized to a receive character. the receiver then samples each bi t time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in th e case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including th e start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (nf) will be set wh en the received character is transferred to the receive data buffer. the falling edge detection l ogic continuously looks for fall ing edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis because some characters do not have any extra falling edges anywhe re in the character frame. in the case of a framing error, pr ovided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new charac ters until the framing error flag is cleared. the receive shift register continues to f unction, but a complete character cannot transfer to the receive data buffer if fe is still set. 14.3.3.2 receiver wakeup operation receiver wakeup is a hardware mech anism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu bit is set, the status flags associated with th e receiver (with the exception of the idle bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 265 message characters. at the end of a message, or at the beginning of the ne xt message, all receivers automatically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 idle-line wakeup when wake = 0, the receiver is configured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detect s a full character time of the idle-l ine level. the m control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle ar e needed to constitute a full character time (10 or 11 bit times becaus e of the start and stop bits). when rwu is one and rwuid is ze ro, the idle condition that wakes up the receiver does not set the idle flag. the receiver wakes up and waits for the first da ta character of the next message which will set the rdrf flag and generate an interrupt if enabled. when rwuid is one, any idle condition sets the idle flag and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit se lects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit a nd any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 address-mark wakeup when wake = 1, the receiver is configured for a ddress-mark wakeup. in this mode, rwu is cleared automatically when the receiver detect s a logic 1 in the most significant bi t of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wakeup allows messages to contain idle characters but re quires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf flag. in this case the ch aracter with the msb set is received even though the receiver was sleeping during most of this character time. 14.3.4 interrupts and status flags the sci system has three se parate interrupt vectors to reduce the amount of softwa re needed to isolate the cause of the interrupt. one interrupt vector is associated with th e transmitter for tdre and tc events. another interrupt vector is associ ated with the receiver for rdrf, idle, rxedgif and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separately masked by local interr upt enable masks. the flags can still be polled by software when the local masks are cleared to disable gene ration of hardware interrupt requests. the sci transmitter has two status fl ags that optionally can generate hard ware interrupt re quests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (t c) indicates that the transmitter is finished transmitting all data, preamble , and break characters and is idle with txd at the inactive level. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a ha rdware interrupt will be requested whenever tc = 1.
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 266 freescale semiconductor instead of hardware interrupts, soft ware polling may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared by reading scixs1 while rdrf = 1 and then reading scixd. when polling is used, this sequence is naturally satisfied in the normal course of the user program. if hardware interrupts are used, scixs1 mu st be read in the interrupt servi ce routine (isr). normally, this is done in the isr anyway to check for receive erro rs, so the sequence is automatically satisfied. the idle status flag includes logic th at prevents it from ge tting set repeatedly when the rxd line remains idle for an extended period of time . idle is cleared by reading scixs1 while idle = 1 and then reading scixd. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received character that caused rdrf to be set, the error flags ? noise flag (nf), framing error (fe) , and parity error flag (pf) ? get set at the same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is rea dy to be transferred from the receive shifter to the receive data buffer, the overrun (or) flag gets set inst ead the data along with any associated nf, fe, or pf condition is lost. at any time, an active edge on th e rxd serial data input pin causes the rxedgif flag to set. the rxedgif flag is cleared by writing a ?1? to it. this function doe s depend on the receiver being enabled (re = 1). 14.3.5 additional sci functions the following sections descri be additional sci functions. 14.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be conf igured to operate in 9-bi t data mode by setting the m control bit in scixc1. in 9-bit m ode, there is a ninth data bit to th e left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scixc3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. if the bit value to be transm itted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker.
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 267 14.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci regist er data is lost and must be re-initialized upon reco very from these two stop modes. no sci module regi sters are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode , but not in stop2. . an active edge on the receive input brings the cpu out of stop3 mode if the interrupt is not masked (rxedgie = 1). note, because the clocks are halted, the sci module will resume operation upon exit from stop (only in stop3 mode). software should ensure stop mode is not entered while ther e is a character being transmitted out of or received into the sci module. 14.3.5.3 loop mode when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is someti mes used to check software, independent of connections in the external system, to help isolate system pr oblems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 14.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). single- wire mode is used to implemen t a half-duplex serial connection. the receiver is internally connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the tx dir bit in scixc3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmit ter is temporarily disconnected from the txd pin so an external de vice can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wi re mode, the internal l oop back connection from the transmitter to the receiver causes the receiver to receive characte rs that are sent out by the transmitter.
serial communications interface (s08sciv4) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 268 freescale semiconductor
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 269 chapter 15 real-time counter (s08rtcv1) 15.1 introduction the rtc module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one progr ammable periodic interrupt. this module can be used for time-of-day, calendar or any task scheduling functi ons. it can also se rve as a cyclic wake up from low power modes without the need of external components.
chapter 15 real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 270 freescale semiconductor figure 15-1. mc9s08el32 block diagram highlighting rtc block v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
chapter 15 real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 271
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 272 freescale semiconductor 15.1.1 features features of the rtc module include: ? 8-bit up-counter ? 8-bit modulo match limit ? software controllable periodic interrupt on match ? three software selectable clock sources for input to prescaler with select able binary-based and decimal-based divider values ? 1-khz internal low-power oscillator (lpo) ? external clock (erclk) ? 32-khz internal clock (irclk) 15.1.2 modes of operation this section defines the operation in stop, wait and background debug modes. 15.1.2.1 wait mode the rtc continues to run in wait mode if enabled before executing the appropriate instruction. therefore, the rtc can bring the mcu out of wait mode if the real-time interrupt is enab led. for lowest possible current consumption, the rtc should be stopped by software if not needed as an interrupt source during wait mode. 15.1.2.2 stop modes the rtc continues to run in stop2 or stop3 mode if the rtc is enabled before executing the stop instruction. therefore, the rtc can bring the mcu out of st op modes with no external components, if the real-time interrupt is enabled. the lpo clock can be used in stop2 and stop3 modes. erclk and irclk clocks are only available in stop3 mode. power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the mcu from stop modes. 15.1.2.3 active background mode the rtc suspends all counting duri ng active background mode until the microcontroll er returns to normal user operating mode. counti ng resumes from the suspe nded value as long as the rtcmod register is not written and the rtcps and rt clks bits are not altered.
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 273 15.1.3 block diagram the block diagram for the rtc module is shown in figure 15-2 . figure 15-2. real-time coun ter (rtc) block diagram 15.2 external signal description the rtc does not include any off-chip signals. 15.3 register definition the rtc includes a status and control register, an 8- bit counter register, and an 8-bit modulo register. refer to the direct-page register summary in the memo ry section of this document for the absolute address assignments for all rtc registers.this section refers to registers and control bi ts only by their names and relative address offsets. table 15-1 is a summary of rtc registers. table 15-1. rtc register summary name 7 6 5 4 3210 rtcsc r rtif rtclks rtie rtcps w rtccnt r rtccnt w rtcmod r rtcmod w clock source select prescaler divide-by 8-bit counter (rtccnt) 8-bit modulo (rtcmod) 8-bit comparator rtif rtie background v dd rtc interrupt request d q r e lpo rtc clock mode erclk irclk rtclks write 1 to rtif rtcps rtclks[0]
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 274 freescale semiconductor 15.3.1 rtc status and co ntrol register (rtcsc) rtcsc contains the real-time interrupt status flag (rtif), the clock se lect bits (rtclks), the real-time interrupt enable bit (rtie), and the prescaler select bits (rtcps). 7 6543210 r rtif rtclks rtie rtcps w reset: 0 0 0 0 0 0 0 0 figure 15-3. rtc status and control register (rtcsc) table 15-2. rtcsc field descriptions field description 7 rtif real-time interrupt flag this status bit indicates the rt c counter register reached the value in the rtc modulo register. writing a logic 0 has no effect. writing a logic 1 clears the bit and the real-time interrupt request. reset clears rtif. 0 rtc counter has not reached the value in the rtc modulo register. 1 rtc counter has reached the value in the rtc modulo register. 6 ? 5 rtclks real-time clock source select. these two read/write bits select the clock source input to the rtc prescaler. changing the clock source clears the prescaler and rt ccnt counters. when selecting a clock source, ensure that the clock source is properly enabled (if applicab le) to ensure correct operation of the rtc. reset clears rtclks. 00 real-time clock source is the 1-khz low power oscillator (lpo) 01 real-time clock source is the external clock (erclk) 1x real-time clock source is the internal clock (irclk) 4 rtie real-time interrupt enable. th is read/write bit enables real-time interrupts. if rtie is set, then an interrupt is generated when rtif is set. reset clears rtie. 0 real-time interrupt requests are disabled. use software polling. 1 real-time interrupt requests are enabled. 3?0 rtcps real-time clock prescaler select. these four read/write bits select binary-based or decimal-based divide-by values for the clock source. see table 15-3 . changing the prescaler value clears the prescaler and rtccnt counters. reset clears rtcps. table 15-3. rtc prescaler divide-by values rtclks[0] rtcps 0 1 2 3 4 5 6 7 8 9 101112 13 14 15 0 off 2 3 2 5 2 6 2 7 2 8 2 9 2 10 12 2 2 10 2 4 10 2 5x10 2 10 3 1 off 2 10 2 11 2 12 2 13 2 14 2 15 2 16 10 3 2x10 3 5x10 3 10 4 2x10 4 5x10 4 10 5 2x10 5
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 275 15.3.2 rtc counter register (rtccnt) rtccnt is the read-only value of the current rtc count of the 8-bit counter. 15.3.3 rtc modulo register (rtcmod) 15.4 functional description the rtc is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-b ased and decimal-based selectable values. the module also contains software selectable interrupt logic. after any mcu reset, the counter is stopped and reset to 0x 00, the modulus register is set to 0x00, and the prescaler is off. the 1-khz internal oscillator clock is selected as the default clock source. to start the prescaler, write any value other than zer o to the prescaler select bits (rtcps). three clock sources are software selectable: the low power oscillator clock (lpo), the external clock (erclk), and the internal clock (irclk). the rtc cl ock select bits (rtclks) select the desired clock source. if a different value is written to rtclks, the prescaler and rtccnt counters are reset to 0x00. 7 6543210 r rtccnt w reset: 0 0 0 0 0 0 0 0 figure 15-4. rtc counter register (rtccnt) table 15-4. rtccnt field descriptions field description 7:0 rtccnt rtc count. these eight read-only bits c ontain the current value of the 8-bit count er. writes have no effect to this register. reset, writing to rtcmod, or writing differen t values to rtclks and rtcp s clear the count to 0x00. 7 6543210 r rtcmod w reset: 0 0 0 0 0 0 0 0 figure 15-5. rtc modulo register (rtcmod) table 15-5. rtcmod field descriptions field description 7:0 rtcmod rtc modulo. these eight read/write bits contain the modulo value used to reset the count to 0x00 upon a compare match and set the rtif status bit. a value of 0x00 sets the rtif bit on each rising edge of the prescaler output. writing to rtcmod resets the prescaler and the rtccnt counters to 0x00. reset sets the modulo to 0x00.
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 276 freescale semiconductor rtcps and the rtclks[0] bit select the desired divide-by value. if a different value is written to rtcps, the prescaler and rtccnt counters are reset to 0x00. table 15-6 shows different prescaler period values. the rtc modulo register (rtcmod) allows the compare value to be set to any value from 0x00 to 0xff. when the counter is active, the count er increments at the se lected rate until the count matches the modulo value. when these values match, the counter resets to 0x00 and continues counting. th e real-time interrupt flag (rtif) is set when a match occurs. the flag sets on the transition from the modulo value to 0x00. writing to rtcmod resets the presca ler and the rtccnt counters to 0x00. the rtc allows for an interrupt to be generated when rtif is set. to enable the real-time interrupt, set the real-time interrupt enable bit (rtie) in rt csc. rtif is cleared by writing a 1 to rtif. 15.4.1 rtc operation example this section shows an example of the rtc operation as the counter reaches a matching value from the modulo register. table 15-6. prescaler period rtcps 1-khz internal clock (rtclks = 00) 1-mhz external clock (rtclks = 01) 32-khz internal clock (rtclks = 10) 32-khz internal clock (rtclks = 11) 0000 off off off off 0001 8 ms 1.024 ms 250 s3 2 m s 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.096 ms 2 ms 128 ms 0100 128 ms 8.192 ms 4 ms 256 ms 0101 256 ms 16.4 ms 8 ms 512 ms 0110 512 ms 32.8 ms 16 ms 1.024 s 0111 1.024 s 65.5 ms 32 ms 2.048 s 1000 1 ms 1 ms 31.25 s 31.25 ms 1001 2 ms 2 ms 62.5 s6 2 . 5 m s 1010 4 ms 5 ms 125 s 156.25 ms 1011 10 ms 10 ms 312.5 s 312.5 ms 1100 16 ms 20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 1 s 0.2 s 31.25 ms 6.25 s
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 277 figure 15-6. rtc counter overflow example in the example of figure 15-6 , the selected clock source is the 1-khz internal oscillator clock source. the prescaler (rtcps) is set to 0xa or divide-by-4. the modulo value in the rtcmod register is set to 0x55. when the counter, rtccnt, reaches the modulo value of 0x55, the counter overflows to 0x00 and continues counting. the real-time interrupt flag, rt if, sets when the counter value changes from 0x55 to 0x00. a real-time interrupt is generated wh en rtif is set, if rtie is set. 15.5 initialization/application information this section provides example code to give some basic direction to a user on how to initialize and configure the rtc module. the example so ftware is implemented in c language. the example below shows how to implement time of day with the rtc using the 1-khz clock source to achieve the lowest possible power consumption. because the 1-khz clock so urce is not as accurate as a crystal, software can be added for any adjustments. for accuracy without adjust ments at the expense of additional power consumption, the external clock (erclk) or the internal clock (i rclk) can be selected with appropriate presca ler and modulo values. /* initialize the elapsed time counters */ seconds = 0; minutes = 0; hours = 0; days=0; /* configure rtc to interrupt every 1 second from 1-khz clock source */ rtcmod.byte = 0x00; rtcsc.byte = 0x1f; /********************************************************************** function name : rtc_isr notes : interrupt service routine for rtc module. **********************************************************************/ 0x55 0x55 0x54 0x53 0x52 0x00 0x01 rtcmod rtif rtccnt rtc clock (rtcps = 0xa) internal 1-khz clock source
real-time counter (s08rtcv1) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 278 freescale semiconductor #pragma trap_proc void rtc_isr(void) { /* clear the interrupt flag */ rtcsc.byte = rtcsc.byte | 0x80; /* rtc interrupts every 1 second */ seconds++; /* 60 seconds in a minute */ if (seconds > 59){ minutes++; seconds = 0; } /* 60 minutes in an hour */ if (minutes > 59){ hours++; minutes = 0; } /* 24 hours in a day */ if (hours > 23){ days ++; hours = 0; }
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 279 chapter 16 timer pulse-width modulator (s08tpmv2) 16.1 introduction the tpm uses one input/output (i/o) pin per channel, tpmxchn where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 0?4). the tpm sh ares its i/o pins with general-purpose i/o port pins (refer to the pins and connections chapter for more information). all mc9s08el32 series and mc9s08sl16 series mcus have two tpm modules. in all packages, tpm2 is 2-channel. the number of channels availabl e in tpm1 depends on the device, as shown in table 16-1 : t table 16-1. mc9s08el32 series and mc9s08sl16 series features by mcu and package feature 9s08el32 9s08el16 9s08sl16 9s08sl8 pin quantity 2820282028202820 package type tssop tssop tssop tssop tssop tssop tssop tssop tpm1 channels 4 2 tpm2 channels 2 2
chapter 16 timer pulse-width modulator (s08tpmv2) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 280 freescale semiconductor figure 16-1. mc9s08el32 block diag ram highlighting tpm block and pins v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 281 16.1.1 features the tpm includes these distinctive features: ? one to eight channels: ? each channel may be input capture, output compare, or edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs ? module may be configured for buffered, center-aligned pulse-w idth-modulation (cpwm) on all channels ? timer clock source selectable as prescaled bus cl ock, fixed system clock, or an external clock pin ? prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 ? fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit ? external clock pin may be shared with any timer channel pin or a separated input pin ? 16-bit free-running or modulo up/down count operation ? timer system enable ? one interrupt per channel pl us terminal count interrupt 16.1.2 modes of operation in general, tpm channels may be i ndependently configured to operate in input capture, output compare, or edge-aligned pwm modes. a control bit allows the whole tpm (all ch annels) to switch to center-aligned pwm mode. when cent er-aligned pwm mode is selected, input capture, output compare, and edge-aligned pwm functions are not available on any channels of this tpm module. when the microcontroller is in active bdm ba ckground or bdm foreground m ode, the tpm temporarily suspends all counting until the micr ocontroller returns to normal user operating mode. during stop mode, all system clocks, including the main oscillator, are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. provided the tpm does not need to produce a real time reference or provide the interrupt source(s) need ed to wake the mcu from wait mode, the user can save power by disab ling tpm functions before entering wait mode. ? input capture mode when a selected edge event occurs on the associat ed mcu pin, the current va lue of the 16-bit timer counter is captured into the channel value register and an interrupt flag bit is set. rising edges, falling edges, any edge, or no edge (disable cha nnel) may be selected as the active edge which triggers the input capture. ? output compare mode when the value in the timer counter register matc hes the channel value register, an interrupt flag bit is set, and a selected output action is for ced on the associated mcu pin. the output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions).
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 282 freescale semiconductor ? edge-aligned pwm mode the value of a 16-bit modulo regist er plus 1 sets the period of the pwm output signal. the channel value register sets the duty cy cle of the pwm output signal. the user may also choose the polarity of the pwm output signal. interrupts are available at the end of the period and at the duty-cycle transition point. this type of pwm signal is calle d edge-aligned because th e leading edges of all pwm signals are aligned with the beginning of the period, which is th e same for all channels within a tpm. ? center-aligned pwm mode twice the value of a 16-bit modulo register sets the period of the pwm output, and the channel-value register sets th e half-duty-cycle duration. the timer counter counts up until it reaches the modulo value and then counts down unt il it reaches zero. as the count matches the channel value register while counting down, the pwm output becomes active. when the count matches the channel value register while countin g up, the pwm output becomes inactive. this type of pwm signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. this t ype of pwm is required for types of motors used in small appliances. this is a high-level description onl y. detailed descriptions of opera ting modes are in later sections. 16.1.3 block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn (timer channel n) where n is the channel number (1-8). the tpm shares its i/o pins with general purpos e i/o port pins (refer to i/o pin descriptions in full-chip specification for th e specific chip implementation). figure 16-2 shows the tpm structure. the central component of the tpm is the 16-bit counter that can operate as a free-running counter or a modulo up/ down counter. the tpm counter (when operating in normal up-counting mode) provides the timing referenc e for the input capture, output compare, and edge-aligned pwm functions. the timer counter mo dulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter (the values 0x0000 or 0xffff effectivel y make the counter free running). software can read the counter value at any time wi thout affecting the counti ng sequence. any write to either half of the tpmxcnt counter resets th e counter, regardless of the data value written.
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 283 figure 16-2. tpm block diagram prescale and select 16-bit comparator ps2:ps1:ps0 tof toie inter- 16-bit counter rupt logic 16-bit comparator 16-bit latch els0b els0a port channel 0 ch0ie ch0f logic inter- rupt logic cpwms ms0b ms0a counter reset clksb:clksa 31, 2, 4, 8, 16, 32, 64, bus clock fixed system clock external clock sync 16-bit comparator 16-bit latch channel 1 els1b els1a ch1ie ch1f internal bus port logic inter- rupt logic ms1b ms1a 16-bit comparator 16-bit latch channel 7 els7b els7a ch7ie ch7f port logic inter- rupt logic ms7b ms7a up to 8 channels clock source select off, bus, fixed system clock, ext or 3128 tpmxmodh:tpmxmodl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxch0 tpmxch1 tpmxc7vh:tpmxc7vl tpmxch7
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 284 freescale semiconductor the tpm channels are programmable independently as input capture, output co mpare, or edge-aligned pwm channels. alternately, the tpm can be configur ed to produce cpwm outputs on all channels. when the tpm is configured for cpwms, the counter ope rates as an up/down count er; input capture, output compare, and epwm func tions are not practical. if a channel is configured as input capture, an internal pullup device may be enabled for that channel. the details of how a module interacts w ith pin controls depends upon the ch ip implementation because the i/o pins and associated general purpose i/ o controls are not part of the modul e. refer to the di scussion of the i/o port logic in a full-chip specification. because center-aligned pwms are usually used to drive 3-phase ac-induction motors and brushless dc motors, they are typically used in sets of three or six channels. 16.2 signal description table 16-2 shows the user-accessible signals for the tpm. the number of channels may be varied from one to eight. when an external cloc k is included, it can be shared with the same pin as any tpm channel; however, it could be connected to a separate input pin. refer to the i/o pin descriptions in full-chip specification for the speci fic chip implementation. refer to documentation for the full-chip for details ab out reset states, port connections, and whether there is any pullup device on these pins. tpm channel pins can be associated with general purpose i/ o pins and have passiv e pullup devices which can be enabled with a control bit when the tpm or general purpose i/o controls have configured the associated pin as an input. when no tpm function is enabled to us e a corresponding pin, the pin reverts to being controlled by general purpose i/o controls, including the port-da ta and data-direction registers. immediately after reset, no tpm functions are enabled, so all associated pins revert to general purpose i/o control. 16.2.1 detailed signal descriptions this section describes each user-acce ssible pin signal in detail. although table 16-2 grouped all channel pins together, any tpm pin can be sh ared with the external clock source signal. since i/o pin logic is not part of the tpm, refer to full-ch ip documentation for a specific derivative for more details about the interaction of tpm pin functions a nd general purpose i/o controls incl uding port data, data direction, and pullup controls. table 16-2. signal properties name function extclk 1 1 when preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. external clock source which may be selected to drive the tpm counter. tpmxchn 2 2 n=channel number (1 to 8) i/o pin associated with tpm channel n
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 285 16.2.1.1 extclk ? external clock source control bits in the timer status a nd control register allow the user to select nothing (tim er disable), the bus-rate clock (the normal de fault source), a crystal-related clock, or an external clock as the clock which drives the tpm prescaler and subsequently the 16-bit tpm counter . the external clock source is synchronized in the tpm. th e bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the fre quency of the bus-rate clock, to meet nyquist criteria and allowing for jitter. the external clock signal shares the same pin as a ch annel i/o pin, so the channel pin will not be usable for channel i/o function when selected as the external cl ock source. it is the user?s responsibility to avoid such settings. if this pin is used as an external clock source (clksb:clksa = 1:1), the channel can still be used in output compare mode as a software timer (elsnb:elsna = 0:0). 16.2.1.2 tpmxchn ? tpm channel n i/o pin(s) each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the channel configuration. the tpm pins share with general purpose i/o pins, where each pin has a port data register bit, and a data di rection control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. the tpm channel does not control th e i/o pin when (elsnb:elsna = 0:0) or when (clksb:clksa = 0:0) so it normally reverts to general purpose i/ o control. when cpwms = 1 (and elsnb:elsna not = 0:0), all channels within the tpm are configured for center-aligned pwm and the tpmxchn pins are all controlled by the tpm system. when cpwms=0, the msnb:msna control bits determine whether the channel is configured for input captur e, output compare, or edge-aligned pwm. when a channel is configured for input capture (cpwms=0, msnb :msna = 0:0 and elsnb:elsna not = 0:0), the tpmxchn pin is forced to act as an e dge-sensitive input to the tpm. elsnb:elsna control bits determine what polarity edge or edges will trigger input-capture events. a synchronizer based on the bus clock is used to synchronize i nput edges to the bus cl ock. this implies the minimum pulse width?that can be reliably detected?on an input capture pin is four bus clock periods (with ideal cloc k pulses as near as two bus clocks can be detected). tpm uses this pi n as an input capture inpu t to override the port data and data direction controls for the same pin. when a channel is configured for output comp are (cpwms=0, msnb:msna = 0:1 and elsnb:elsna not = 0:0), the associated data direction control is overridden, the tp mxchn pin is considered an output controlled by the tpm, and the elsnb:elsna contro l bits determine how the pin is controlled. the remaining three combinations of elsnb:elsna dete rmine whether the tpmxchn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. when the output compare toggle mode is initially select ed, the previous value on th e pin is driven out until the next output compare event?then the pin is toggled.
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 286 freescale semiconductor when a channel is configured for edge-aligne d pwm (cpwms=0, msnb=1 and elsnb:elsna not = 0:0), the data direction is overridden, the tpmxchn pin is forced to be an output controlled by the tpm, and elsna controls the polarity of the pwm out put signal on the pin. when elsnb:elsna=1:0, the tpmxchn pin is forced high at th e start of each new period (tpmxcnt=0x0000), and the pin is forced low when the channel value register matches the timer counter. when elsna=1, the tpmxchn pin is forced low at the start of each new period (tpm xcnt=0x0000), and the pin is forced high when the channel value register matches the timer counter. figure 16-3. high-true pulse of an edge-aligned pwm figure 16-4. low-true pulse of an edge-aligned pwm chnf bit tof bit 0 ... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit 0 ... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 287 when the tpm is configur ed for center-aligned pwm (and elsnb: elsna not = 0:0), th e data direction for all channels in this tpm are overridden, the tpmxchn pins are forc ed to be outputs controlled by the tpm, and the elsna bits control the polarity of each tpmxchn output. if elsnb:elsna=1:0, the corresponding tpmxchn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the tpmxchn pin is set when the timer counter is counting down, and the channel value register matche s the timer counter. if elsna=1, the corresponding tpmxchn pin is set when the timer counter is counting up and the chan nel value register matches the timer counter; the tpmxchn pin is cleared wh en the timer counter is counting down and the cha nnel value register matches the timer counter. figure 16-5. high-true pulse of a center-aligned pwm figure 16-6. low-true pulse of a center-aligned pwm chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 288 freescale semiconductor 16.3 register definition this section consists of register descriptions in address order. a typical mcu syst em may contain multiple tpms, and each tpm may have one to eight channels, so register names include placeholder characters to identify which tpm and which channel is being refe renced. for example, tpmxcnsc refers to timer (tpm) x, channel n. tpm1c2sc would be the status and control register for channel 2 of timer 1. 16.3.1 tpm status and control register (tpmxsc) tpmxsc contains the overflow status flag and control bits used to configure the interrupt enable, tpm configuration, clock source, and prescale factor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w0 r e s e t00000000 figure 16-7. tpm status and control register (tpmxsc) table 16-3. tpmxsc field descriptions field description 7 tof timer overflow flag. this read/write flag is set when the tpm counter resets to 0x0000 after reaching the modulo value programmed in the tpm counter modulo register s. clear tof by reading the tpm status and control register when tof is set and then writing a logic 0 to tof. if another tpm overflow occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. this is done so a tof interrupt request cannot be lost during the clearing sequence for a previous tof. reset clears tof. writing a logic 1 to tof has no effect. 0 tpm counter has not reached modulo value or overflow 1 tpm counter has overflowed 6 toie timer overflow interrupt enable. this read/write bit enables tpm overflow interrupts. if toie is set, an interrupt is generated when tof equals one. reset clears toie. 0 tof interrupts inhibited (use for software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select. when present, this read/wri te bit selects cpwm operating mode. by default, the tpm operates in up-counting mode for input capture, out put compare, and edge-aligned pwm functions. setting cpwms reconfigures the tpm to operate in up/down counting mode for cpwm functions. reset clears cpwms. 0 all channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each ch annel?s status and control register. 1 all channels operate in center-aligned pwm mode.
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 289 16.3.2 tpm-counter regist ers (tpmxcnth:tpmxcntl) the two read-only tpm counter regist ers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latche s the contents of both byt es into a buffer where they remain latched until the other half is read. this allows coherent 16-bit reads in either big-endian or little-endian order which makes th is more friendly to various comp iler implementations. the coherency mechanism is automatically restarted by an mcu reset or any write to the time r status/control register (tpmxsc). 4?3 clks[b:a] clock source selects. as shown in table 16-4 , this 2-bit field is used to disabl e the tpm system or select one of three clock sources to drive the counter prescaler. the fixed system clock source is only meaningful in systems with a pll-based or fll-based system cl ock. when there is no pll or fll, the fixed-system clock source is the same as the bus rate clock. the external source is synchronized to the bus clock by tpm module, and the fixed system clock source (when a pll or fll is present) is synchronized to the bus clock by an on-chip synchronization circuit. when a pll or fll is present but not e nabled, the fixed-system clock source is the same as the bus-rate clock. 2?0 ps[2:0] prescale factor select. this 3-bit field selects one of 8 division factors for the tpm clock input as shown in ta b l e 1 6 - 5 . this prescaler is located after any clock source syn chronization or clock source selection so it affects the clock source selected to drive the tpm system. the new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. table 16-4. tpm-clock-source selection clksb:clksa tpm clock so urce to prescaler input 00 no clock selected (tpm counter disable) 01 bus rate clock 10 fixed system clock 11 external source table 16-5. prescale factor selection ps2:ps1:ps0 tpm clock source divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 table 16-3. tpmxsc field descriptions (continued) field description
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 290 freescale semiconductor reset clears the tpm count er registers. writing a ny value to tpmxcnth or tpmxcntl also clears the tpm counter (tpmxcnth:tpmxcntl) and resets the coherency mechanism, regardless of the data involved in the write. when bdm is active, the time r counter is frozen (this is the value that will be re ad by user); the coherency mechanism is frozen such that the buffer latches rema in in the state they were in when the bdm became active, even if one or both counter halves are read whil e bdm is active. this assu res that if the user was in the middle of reading a 16- bit register when bdm beca me active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. in bdm mode, writing any value to tpmxsc, tpmx cnth or tpmxcntl registers resets the read coherency mechanism of the tpmxcn th:l registers, regardless of the data involved in the write. 16.3.3 tpm counter modulo re gisters (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock, and the overflow flag (tof) becomes set. writing to tpmxmodh or tpmxmodl i nhibits the tof bit and overflow interrupts until the other byte is written. reset sets the tp m counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). writing to either byte (tpmxmodh or tpmxmodl) latches the value into a buffer and the registers are updated with the value of their write buffer acco rding to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), then the registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), then the registers are updated after both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff the latching mechanism may be manually reset by writing to the tp mxsc address (w hether bdm is active or not). 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter r e s e t00000000 figure 16-8. tpm counter register high (tpmxcnth) 76543210 rb i t 7654321b i t 0 w any write to tpmxcntl clears the 16-bit counter r e s e t00000000 figure 16-9. tpm counter register low (tpmxcntl)
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 291 when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxsc register) such that the buffer latches remain in the state they were in when the bdm becam e active, even if one or both halves of the modulo register are written while bdm is active. a ny write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while bdm is active. reset the tpm counter before writin g to the tpm modulo registers to a void confusion about when the first counter overflow will occur. 16.3.4 tpm channel n status an d control register (tpmxcnsc) tpmxcnsc contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 76543210 r bit 15 14 13 12 11 10 9 bit 8 w r e s e t00000000 figure 16-10. tpm counter modulo register high (tpmxmodh) 76543210 r b i t 7654321b i t 0 w r e s e t00000000 figure 16-11. tpm counter modulo register low (tpmxmodl) 76543210 rchnf chnie msnb msna elsnb elsna 00 w0 r e s e t00000000 = unimplemented or reserved figure 16-12. tpm channel n status and control register (tpmxcnsc)
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 292 freescale semiconductor table 16-6. tpmxcnsc field descriptions field description 7 chnf channel n flag. when channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. when channel n is an output com pare or edge-aligned/center-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. when channel n is an edge-aligned/center-aligned pwm channel and the duty cycle is set to 0% or 100%, chnf will not be set even when the value in the tpm counter registers ma tches the value in the tpm channel n value registers. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a logic 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf remains set after the clear sequence completed for the earlier chnf. this is done so a chnf interr upt request cannot be lost due to clearing a previous chnf. reset clears the chnf bit. writing a logic 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event on channel n 6 chnie channel n interrupt enable. this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use for software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n. when cpwms=0, ms nb=1 configures tpm channel n for edge-aligned pwm mode. refer to the summary of channel mode and setup controls in table 16-7 . 4 msna mode select a for tpm channel n. when cpwms=0 and msnb=0, msna configures tpm channel n for input-capture mode or output compare mode. refer to ta bl e 1 6 - 7 for a summary of channel mode and setup controls. note: if the associated port pin is not stable for at least two bus cl ock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3?2 elsnb elsna edge/level select bits. depending upon the operating mo de for the timer channel as set by cpwms:msnb:msna and shown in table 16-7 , these bits select the polarity of the input e dge that triggers an input capture event, select the level that will be driven in response to an output co mpare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 configures the related timer pin as a general purpose i/o pin not related to any timer functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. table 16-7. mode, edge, and level selection cpwms msnb:msna elsnb:el sna mode configuration x xx 00 pin not used for tpm - revert to general purpose i/o or other peripheral control
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 293 16.3.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) these read/write register s contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pw m functions. the channel registers are cleared by reset. in input capture mode, reading eith er byte (tpmxcnvh or tpmxcnvl) la tches the contents of both bytes into a buffer where they remain latched until the othe r half is read. this latching mechanism also resets 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 01 output compare toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w r e s e t00000000 figure 16-13. tpm channel value register high (tpmxcnvh) 76543210 r b i t 7654321b i t 0 w r e s e t00000000 figure 16-14. tpm channel value register low (tpmxcnvl) table 16-7. mode, edge, and level selection cpwms msnb:msna elsnb:el sna mode configuration
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 294 freescale semiconductor (becomes unlatched) when the tpmxcnsc register is wr itten (whether bdm mode is active or not). any write to the channel registers will be ignored during the input capture mode. when bdm is active, the coherency mechanism is fro zen (unless reset by writi ng to tpmxcnsc register) such that the buffer latches remain in the state they were in when the bdm becam e active, even if one or both halves of the channel register are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. the value read from the tpmxcnvh and tpmxcnvl registers in bdm mode is the value of these registers and not the value of their read buffer. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. after both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of clksb:clksa bits and the selected mode, so: ? if (clksb:clksa = 0:0), then the registers are updated when the second byte is written. ? if (clksb:clksa not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the tpm counter (end of the prescaler counting). ? if (clksb:clksa not = 0:0 and in epwm or cpwm modes), then the registers are updated after the both bytes were written, and the tpm count er changes from (tpm xmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if th e tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. the latching mechanism may be manually reset by writing to the tpmxcnsc register (whether bdm mode is active or not). this latchi ng mechanism allows cohe rent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. when bdm is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active even if one or both halves of the channel register are written while bdm is active. any write to the channel regist ers bypasses the buffer latche s and directly write to the channel register while bdm is act ive. the values written to the ch annel register while bdm is active are used for pwm & output compare operation once nor mal execution resumes. writes to the channel registers while bdm is acti ve do not interfere with partial comple tion of a coherency sequence. after the coherency mechanism has been fully exercised, the channel registers ar e updated using the buffered values written (while bdm was not active) by the user. 16.4 functional description all tpm functions are associ ated with a central 16-bit counter which allows flexible selection of the clock source and prescale factor. there is also a 16-bit modulo register associated with the main counter. the cpwms control bit chooses be tween center-aligned pwm operation for all channels in the tpm (cpwms=1) or general purpose ti ming functions (cpwms=0) where each channel can independently be configured to operate in input capture, output co mpare, or edge-aligned pwm mode. the cpwms control bit is located in the main tpm status and control regi ster because it affects all channels within the tpm and influences the wa y the main counter operates. (in cpwm m ode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.)
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 295 the following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend upon the opera ting mode, these topics will be covered in the associated mode explanation sections. 16.4.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, end-of-count overflow, up- counting vs. up/down counting, and manual counter reset. 16.4.1.1 counter clock source the 2-bit field, clksb:clksa, in the timer status a nd control register (tpmxs c) selects one of three possible clock sources or off (which effectively disabl es the tpm). see table 16-4 . after any mcu reset, clksb:clksa=0:0 so no clock source is selected, and the tpm is in a very low power state. these control bits may be read or writ ten at any time and disabling the timer (writing 00 to the clksb:clksa field) does not affect the values in the counter or other timer registers.
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 296 freescale semiconductor the bus rate clock is the main system bus cl ock for the mcu. this clock source requires no synchronization because it is the clock that is used for all inte rnal mcu activities including operation of the cpu and buses. in mcus that have no pll and fll or the pll and fll are not engage d, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. when a pll or fll is present and engaged, a synchronize r is required between the crystal di vided-by two clock source and the timer counter so counter transitions will be properly aligne d to bus-clock transiti ons. a synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. the external clock source may be connected to any tpm ch annel pin. this clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. the bus-rate clock drives the synchronizer; therefore, to meet nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by f our. with ideal clocks the external clock can be as fast as bus clock divided by four. when the external clock source shar es the tpm channel pin, this pin s hould not be used for other channel timing functions. for example, it w ould be ambiguous to configure channel 0 for input capture when the tpm channel 0 pin was also being used as the timer external clock source . (it is the user?s responsibility to avoid such settings.) the tpm channel could still be used in output compare mode for software timing functions (pin controls set not to affect the tpm channel pin). 16.4.1.2 counter overflow and modulo reset an interrupt flag and enable are associated wi th the 16-bit main counter. the flag (tof) is a software-accessible indication that the timer counter has overflowed. th e enable signal selects between software polling (toie=0) where no hardware interrupt is generated, or interrupt-driven operation (toie=1) where a static hardware interrupt is generated whenever the tof flag is equal to one. the conditions causing tof to become set depend on whether the tpm is configured for center-aligned pwm (cpwms=1). in the simplest mode, there is no modulus limit and the tpm is not in cpwms=1 mode. in this case, the 16-bit timer counter counts from 0x0000 th rough 0xffff and overflows to 0x0000 on the next counting clock. tof becomes set at the transition fr om 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the tpm is in center-aligned pwm mode (cpwms=1), the tof flag ge ts set as the counter changes direction at the end of the count valu e set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). this corresponds to the end of a pwm period (the 0x0000 count value corresponds to the center of a period). table 16-8. tpm clock source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (t pm counter disabled) 01 bus rate clock 10 fixed system clock 11 external source
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 297 16.4.1.3 counting modes the main timer counter has two c ounting modes. when center-aligned pwm is selected (cpwms=1), the counter operates in up/down counting mode. otherwise, the counter operates as a simple up counter. as an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is specified, th e counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up count ing. both 0x0000 and th e terminal count value are normal length counts (one tim er clock period long). in this m ode, the timer overflow flag (tof) becomes set at the end of the terminal-count period (a s the count changes to the next lower count value). 16.4.1.4 manual counter reset the main timer counter can be manually reset at any time by writing any value to either half of tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only half of the counter wa s read before resetting the count. 16.4.2 channel mode selection provided cpwms=0, the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and edge-aligned pwm. 16.4.2.1 input capture mode with the input-capture function, the tpm can capture the time at which an exte rnal event occurs. when an active edge occurs on the pin of an input-capture channel, the tpm latches the contents of the tpm counter into the channel-value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. in input capture mode, the tpmxcnvh and tpmxcnvl registers are read only. when either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endi an or little-endian order. the coherency sequence can be manually reset by writing to the channel st atus/control register (tpmxcnsc). an input capture event sets a flag bit (chnf) wh ich may optionally generate a cpu interrupt request. while in bdm, the input ca pture function works as conf igured by the user. when an external event occurs, the tpm latches the contents of the tpm counter (which is frozen because of the bdm mode) into the channel value registers and sets the flag bit. 16.4.2.2 output compare mode with the output-compare function, the tpm can ge nerate timed pulses with programmable position, polarity, duration, and frequency. when the counter reach es the value in the channel-value registers of an output-compare channel, the tpm can se t, clear, or toggle the channel pin.
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 298 freescale semiconductor in output compare mode, values are transferred to th e corresponding timer channel registers only after both 8-bit halves of a 16-bit register ha ve been written and according to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated at the ne xt change of the tpm counter (end of the prescaler counting) after the second byte is written. the coherency sequence can be manually reset by wr iting to the channel st atus/control register (tpmxcnsc). an output compare event sets a flag bit (chnf) wh ich may optionally generate a cpu-interrupt request. 16.4.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counti ng mode of the timer c ounter (cpwms=0) and can be used when other channels in the same tpm ar e configured for input cap ture or output compare functions. the period of this pwm signal is dete rmined by the value of the modulus register (tpmxmodh:tpmxmodl) plus 1. the duty cycle is determined by the setting in the timer channel register (tpmxcnvh:tpmxcn vl). the polarity of this pwm signal is determined by the setting in the elsna control bit. 0% and 100% duty cycle cases are possible. the output compare value in the tpm channel registers determines the pulse wi dth (duty cycle) of the pwm signal ( figure 16-15 ). the time between the modulus overflo w and the output compare is the pulse width. if elsna=0, the counter overflow forces the pwm signal high, and the out put compare forces the pwm signal low. if elsna=1, the c ounter overflow forces the pwm si gnal low, and the output compare forces the pwm signal high. figure 16-15. pwm period and pulse width (elsna=0) when the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel regi ster (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting. this implies that the modulus setting must be less than 0xffff in order to get 100% duty cycle. because the tpm may be used in an 8-bit mcu, the se ttings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxcnvh and tpmxcnvl, actually wr ite to buffer registers. in e dge-aligned pwm mode, values are transferred to the corresponding timer- channel registers according to th e value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if period pulse width overflow overflow overflow output compare output compare output compare tpmxchn
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 299 the tpm counter is a fr ee-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. 16.4.2.4 center-aligned pwm mode this type of pwm output uses th e up/down counting mode of the timer counter (cpwms=1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal while the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff becaus e values outside this ra nge can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) period = 2 x (tpmxmodh:tpmxmodl ); tpmxmodh:tpmxmodl=0x0001-0x7fff if the channel-value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if you do not need to generate 100% duty cycle). this is not a significant limitation. the resu lting period would be much longer than required for normal applications. tpmxmodh:tpmxmodl=0x0000 is a special case that should not be used wi th center-aligned pwm mode. when cpwms=0, this case co rresponds to the counter runni ng free from 0x0000 through 0xffff, but when cpwms=1 the counter needs a valid match to the modulus register so mewhere other than at 0x0000 in order to change directions from up-counting to down-counting. the output compare value in the tpm channel registers (times 2) determines the pulse width (duty cycle) of the cpwm signal ( figure 16-16 ). if elsna=0, a compare occurred while counting up forces the cpwm output signal low and a compare occurred while counting down forc es the output high. the counter counts up until it reaches the modulo se tting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to tw o times tpmxmodh:tpmxmodl. figure 16-16. cpwm period and pulse width (elsna=0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also require d for some types of motor drives. period pulse width count= count= 0 count= output compare (count down) output compare (count up) tpmxchn 2 x tpmxmodh:tpmxmodl 2 x tpmxcnvh:tpmxcnvl tpmxmodh:tpmxmodl tpmxmodh:tpmxmodl
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 300 freescale semiconductor input capture, output compare, a nd edge-aligned pwm functions do not make sense when the counter is operating in up/down counting mode so th is implies that all act ive channels within a tpm must be used in cpwm mode when cpwms=1. the tpm may be used in an 8-bit mc u. the settings in the timer channe l registers are buffered to ensure coherent 16-bit updates and to a void unexpected pwm pulse widths. wr ites to any of the registers tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl , actually write to buffer registers. in center-aligned pwm mode, the tpmxcnvh:l registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff. when tpmxcnth:tpmxcntl=tpmxmodh:tpmxmodl, the tpm can optionally generate a tof interrupt (at the end of this count). writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo re gisters. writing to tpmxcnsc ca ncels any values written to the channel value registers and resets the c oherency mechanism for tpmxcnvh:tpmxcnvl. 16.5 reset overview 16.5.1 general the tpm is reset whenever any mcu reset occurs. 16.5.2 description of reset operation reset clears the tpmxsc register wh ich disables clocks to the tpm a nd disables timer overflow interrupts (toie=0). cpwms, msnb, msna, elsnb, and elsna are all cleared which configures all tpm channels for input-capture operation with the associated pins disconnect ed from i/o pin logic (so all mcu pins related to the tpm revert to general purpose i/o pins). 16.6 interrupts 16.6.1 general the tpm generates an optional interr upt for the main counter overflow a nd an interrupt for each channel. the meaning of channel interrupts depends on each channel?s mode of operation. if the channel is configured for input capture, the in terrupt flag is set ea ch time the selected input capture edge is recognized. if the channel is configur ed for output compare or pwm modes, the interrupt flag is set each time the main timer counter matches the va lue in the 16-bit channel value register.
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 301 all tpm interrupts are listed in table 16-9 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the tpm and getting r ecognized by the separate interrupt processing logic. the tpm module will provide a high-tr ue interrupt signal. vectors and pr iorities are determined at chip integration time in the interrupt module so refer to the user?s guide for th e interrupt module or to the chip?s complete document ation for details. 16.6.2 description of interrupt operation for each interrupt source in the tpm, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input captur e, or output-compare events. this flag may be read (polled) by software to determine that the action has occurred, or an associated enab le bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interr upt will generate whenever the associated interrupt flag equals one. the user?s software must perform a sequence of steps to clear the interrupt flag before retu rning from the interrupt-service routine. tpm interrupt flags are clear ed by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to th e bit. if a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 16.6.2.1 timer overflow in terrupt (tof) description the meaning and details of operation for tof interrupts varies slightly depending upon the mode of operation of the tpm system (gen eral purpose timing functions vers us center-aligned pwm operation). the flag is cleared by the two step sequence described above. 16.6.2.1.1 normal case normally tof is set when the timer counter ch anges from 0xffff to 0x0000. when the tpm is not configured for center-aligned pwm (cpwms=0), tof ge ts set when the timer c ounter changes from the terminal count (the value in th e modulo register) to 0x0000. this case corresponds to the normal meaning of counter overflow. table 16-9. interrupt summary interrupt local enable source description tof toie counter overflow set each time th e timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) chnf chnie channel event an input capt ure or output compare event took place on channel n
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 302 freescale semiconductor 16.6.2.1.2 center-aligned pwm case when cpwms=1, tof gets set when the timer c ounter changes directi on from up-counting to down-counting at the end of the terminal count (the value in the modul o register). in this case the tof corresponds to the end of a pwm period. 16.6.2.2 channel event interrupt description the meaning of channel interrupts depends on the channel?s current m ode (input-capture, output-compare, edge-aligned pwm, or center-aligned pwm). 16.6.2.2.1 input capture events when a channel is configured as an input capture channel, the elsnb:elsna control bits select no edge (off), rising edges, falling edges or any edge as the ed ge which triggers an input capture event. when the selected edge is detected, the interrupt flag is set. the flag is cleared by the two-step sequence described in section 16.6.2, ?description of interrupt operation .? 16.6.2.2.2 output compare events when a channel is configured as an output compare chan nel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. th e flag is cleared by the two-step sequence described section 16.6.2, ?description of interrupt operation .? 16.6.2.2.3 pwm end-of-duty-cycle events for channels configured for pwm operation there are two possibilities. when the channel is configured for edge-aligned pwm, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. wh en the channel is configured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value regi ster. the flag is cleared by the two-step sequence described section 16.6.2, ?description of interrupt operation .? 16.7 the differences from tpm v2 to tpm v3 1. write to tpmxcnth:l registers ( section 16.3.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) ) [se110-tpm case 7] any write to tpmxcnth or tpmxcntl registers in tpm v3 clears the tpm counter (tpmxcnth:l) and the prescaler co unter. instead, in the tpm v2 only the tpm counter is cleared in this case. 2. read of tpmxcnth:l registers ( section 16.3.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) ) ? in tpm v3, any read of tpmxcnth:l register s during bdm mode returns the value of the tpm counter that is frozen. in tpm v2, if only one byte of the tpmxcnth:l registers was read before the bdm mode became active, th en any read of tpmxcnth:l registers during
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 303 bdm mode returns the latched value of tpmxcn th:l from the read buffer instead of the frozen tpm counter value. ? this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxsc, tpmxcnth or tpmxcntl. instead, in these conditions the tpm v2 does not clear this read coherency mechanism. 3. read of tpmxcnvh:l registers ( section 16.3.5, ?tpm channel value registers (tpmxcnvh:tpmxcnvl) ) ? in tpm v3, any read of tpmxcnvh:l register s during bdm mode returns the value of the tpmxcnvh:l register. in tpm v2, if only one byte of the tpmxcnvh:l registers was read before the bdm mode became active, then a ny read of tpmxcnvh:l registers during bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the value in the tpmxcnvh:l registers. ? this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxcnsc. instead, in this condition the tp m v2 does not clear this read coherency mechanism. 4. write to tpmxcnvh:l registers ? input capture mode ( section 16.4.2.1, ?input capture mode ) in this mode the tpm v3 does not allow the writes to tpmxcnvh:l registers. instead, the tpm v2 allows these writes. ? output compare mode ( section 16.4.2.2, ?output compare mode ) in this mode and if (clksb:clksa not = 0:0), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer at the next change of the tpm counter (end of the prescaler counting) after the se cond byte is written. instead, the tpm v2 always updates these registers when their second byte is written. the following procedure can be used in the tpm v3 to verify if th e tpmxcnvh:l registers were updated with the new value th at was written to these register s (value in their write buffer). ... write the new value to tpmxcnvh:l; read tpmxcnvh and tpmxcnvl registers; while (the read value of tp mxcnvh:l is different from the new value written to tpmxcnvh:l) begin read again tpmxcnvh and tpmxcnvl; end ... in this point, the tpmxcnvh:l registers were updated, so the program can continue and, for example, write to tpmxc0sc without can celling the previous write to tpmxcnvh:l registers. ? edge-aligned pwm ( section 16.4.2.3, ?edge-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes we re written and when the
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 304 freescale semiconductor tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to $0000. ? center-aligned pwm ( section 16.4.2.4, ?center-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes we re written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to (tpmxmodh:l - 1). 5. center-aligned pwm ( section 16.4.2.4, ?center-aligned pwm mode ) ? tpmxcnvh:l = tpmxmodh:l [se110-tpm case 1] in this case, the tpm v3 produces 100% duty cycle. instead, the tpm v2 produces 0% duty cycle. ? tpmxcnvh:l = (tpmxmodh:l - 1) [se110-tpm case 2] in this case, the tpm v3 produces almost 100% duty cycle. in stead, the tpm v2 produces 0% duty cycle. ? tpmxcnvh:l is changed from 0x0000 to a non-zero value [se110-tpm case 3 and 5] in this case, the tpm v3 waits for the start of a new pwm period to be gin using the new duty cycle setting. instead, the tpm v2 changes the channel output at the middle of the current pwm period (when the count reaches 0x0000). ? tpmxcnvh:l is changed from a non-zero value to 0x0000 [se110-tpm case 4] in this case, the tpm v3 finishes the curren t pwm period using the old duty cycle setting. instead, the tpm v2 finishes the current pw m period using the new duty cycle setting. 6. write to tpmxmodh:l re gisters in bdm mode ( section 16.3.3, ?tpm counter modulo registers (tpmxmodh:tpmxmodl) ) in the tpm v3 a write to tpmxsc register in bdm mode clears the write coherency mechanism of tpmxmodh:l registers. instead, in the tpm v2 this coherency mechanism is not cleared when there is a write to tpmxsc register. 7. update of epwm signal when clksb:clksa = 00 in the tpm v3 if clksb:clksa = 00, then the ep wm signal in the channel output is not update (it is frozen while clksb:clksa = 00). instead , in the tpm v2 the epwm signal is updated at the next rising edge of bus clock af ter a write to tpmxcnsc register. the figure 0-1 and figure 0-2 show when the epwm signal s generated by tpm v2 and tpm v3 after the reset (clksb:clksa = 00) and if there is a write to tpmxcnsc register.
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 305 figure 0-1. generation of high-true epwm signal by tpm v2 and v3 after the reset elsnb:elsna bits clksb:clksa bits 0 tpmxmodh:tpmxmodl = 0x0007 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmv2 tpmxchn epwm mode 00 00 10 bus clock 01 1234567 01 2 chnf bit msnb:msna bits 00 10 (in tpmv2 and tpmv3) tpmv3 tpmxchn ... reset (active low)
timer/pwm module (s08tpmv3) mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 306 freescale semiconductor figure 0-2. generation of low-true epwm signal by tpm v2 and v3 after the reset the following procedure can be used in tpm v3 (when the channel pin is also a port pin) to emulate the high-true epwm generated by tpm v2 after the reset. ... configure the channel pin as output port pin and set the output pin; configure the channel to generate the epwm signal but keep elsnb:elsna as 00; configure the other registers (tpmxmo dh, tpmxmodl, tpmxcnvh, tpmxcnvl, ...); configure clksb:clksa bits (tpm v3 starts to generate the high-true epwm signal, however tpm does not control the channel pin, so the epwm signal is not available); wait until the tof is set (or use the tof interrupt); enable the channel output by configuring elsnb:elsna bits (now epwm signal is available); ... elsnb:elsna bits clksb:clksa bits 0 tpmxmodh:tpmxmodl = 0x0007 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmv2 tpmxchn epwm mode 00 00 01 bus clock 01 1234567 01 2 chnf bit msnb:msna bits 00 10 (in tpmv2 and tpmv3) tpmv3 tpmxchn ... reset (active low)
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 307 chapter 17 development support 17.1 introduction development support systems in the hcs08 include the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provides a singl e-wire debug interface to the target mcu that provides a convenient inte rface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allo ws non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoint s, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through comma nds fed into the target mcu vi a the single-wire background debug interface. the debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 forcing active background the method for forcing active background mode depe nds on the specific hcs08 derivative. for the mc9s08el32 series and mc9s08sl16 series, you can force active background after a power-on reset by holding the bkgd pin low as the device exits the rese t condition (independent of the reset source). you can also force active b ackground by driving bkgd low immediatel y after a serial background command that writes a one to the bdfr bi t in the sbdfr register. if no debug pod is connected to the bkgd pin, the mcu always resets into normal operating mode.
development supportchapter 17 development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 308 freescale semiconductor figure 17-1. mc9s08el32 block diagram highlighting dbg block v ss iic module (iic) serial peripheral interface module (spi) user flash user ram 32k / 16k hcs08 core cpu bdc 2-channel timer/pwm module (tpm2) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop lvd oscillator (xosc) internal clock source (ics) reset v refh 1024 bytes interface (sci) serial communications xtal extal 4-channel timer/pwm module (tpm1) real-time counter in-circuit emulator (ice) bkgd/ms pta3/pia3/scl/txd/adp3 pta6/tpm2ch0 pta2/pia2/sda/rxd/acmp1o/adp2 pta1/pia1/tpm2ch0/acmp1?/adp1 pta0/pia0/tpm1ch0/tclk/acmp1+/adp0 pta7/tpm2ch1 ptb3/pib3/scl/mosi/adp7 ptb4/tpm2ch1/miso ptb2/pib2/sda/spsck/adp6 ptb1/pib1/sltxd/txd/adp5 ptb0/pib0/slrxd/rxd/adp4 ptb7/scl/extal ptc3/pic3/tpm1ch3/adp11 ptc4/pic4/adp12 ptc5/pic5/acmp2o/adp13 ptc2/pic2/tpm1ch2/adp10 ptc1/pic1/tpm1ch1/adp9 port c ptc6/pic6/acmp2+/adp14 v dd bkp int analog comparator (acmp2) user eeprom 512 bytes controller (slic) slave lin interface analog-to-digital converter (adc) 16-channel,10-bit 16 = in 20-pin packages, v dda /v refh is internally connected to v dd and v ssa /v refl is internally connected to v ss . v dda / v refl v ssa / debug module (dbg) on-chip (rtc) ptc0/pic0/tpm1ch0/adp8 ptc7/pic7/acmp2?/adp15 ptb6/sda/xtal port b port a ptb5/tpm1ch1/ss analog comparator (acmp1) = not bonded to pins in 20-pin package tclk tclk + ? out + ? out 0 1 2 3 1 0 rxd txd tx rx
development supportchapter 17 development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 309
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 310 freescale semiconductor 17.1.2 features features of the bdc module include: ? single pin for mode selection and background communications ? bdc registers are not located in the memory map ? sync command to determine target communications rate ? non-intrusive commands for memory access ? active background mode comma nds for cpu register access ? go and trace1 commands ? background command can wake cpu from stop or wait modes ? one hardware address breakpoint built into bdc ? oscillator runs in stop mode, if bdc enabled ? cop watchdog disabled while in active background mode features of the ice system include: ? two trigger comparators: two address + read/write (r/w) or one full address + data + r/w ? flexible 8-word by 16-bit fifo (first-in, first-out) buffe r for capture information: ? change-of-flow addresses or ? event-only data ? two types of breakpoints: ? tag breakpoints for instruction opcodes ? force breakpoints for any address access ? nine trigger modes: ? basic: a-only, a or b ? sequence: a then b ? full: a and b data, a and not b data ? event (store data): event- only b, a then event-only b ? range: inside range (a address b), outside range (address < a or address > b) 17.2 background debug controller (bdc) all mcus in the hcs08 family co ntain a single-wire background debug in terface that supports in-circuit programming of on-chip nonvolatile me mory and sophisticated non-intrus ive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: ? active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands al low the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 311 ? non-intrusive commands can be executed at any time even while the user?s program is running. non-intrusive commands allow a user to read or wr ite mcu memory locations or access status and control registers within the background debug controller. typically, a relatively s imple interface pod is used to translat e commands from a host computer into commands for the custom serial interface to the single-wire bac kground debug system. depending on the development tool vendor, this interface pod may use a sta ndard rs-232 serial port, a parallel printer port, or some other type of communicati ons such as a universal serial bu s (usb) to communicate between the host pc and the pod. the pod typically connects to th e target system with ground, the bkgd pin, reset , and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target syst em or to control startup of a target system before the on-chip nonvolatile memory has be en programmed. sometimes v dd can be used to allow the pod to use power from the target system to a void the need for a separa te power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 17-2. bdm tool connector 17.2.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communi cation of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the us er?s application program. this pin is also used to request a timed sync respons e pulse to allow a host deve lopment tool to determine the correct clock frequency for b ackground debug serial communications. bdc serial communications use a cu stom serial protocol first introduced on the m68hc12 family of microcontrollers. this protocol a ssumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is in itiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most significant bit first (msb first). for a detailed descript ion of the communications protocol, refer to section 17.2.2, ?communication details .? if a host is attempting to communi cate with a target mcu that ha s an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync res ponse signal from wh ich the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no ex ternal pullup resistor is required. unlike typical open-drain pins, the ex ternal rc time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. the custom prot ocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmfu l drive level conflicts. refer to section 17.2.2, ?communication details ,? for more detail. 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 312 freescale semiconductor when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode . when a debug pod is connected to bkgd it is possible to force the mcu into active background mode after reset. the speci fic conditions for forci ng active background depend upon the hcs08 derivative (refer to the introduction to this developm ent support section). it is not necessary to reset the target mcu to communi cate with it through the background debug interface. 17.2.2 communication details the bdc serial interface requires the external contro ller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external cont roller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an extern al controller or by the mcu. data is transferred msb first at 16 bdc clock cycles pe r bit (nominal speed). th e interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecti ng the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and c ontrol register allows th e user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or lo w level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 313 figure 17-3 shows an external host trans mitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0- to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively driv es the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to tr eat the line as an open-drain signal during this period. figure 17-3. bdc ho st-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 314 freescale semiconductor figure 17-4 shows the host receiving a logic 1 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived star t of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brie f active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level a bout 10 cycles after it started the bit time. figure 17-4. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 315 figure 17-5 shows the host receiving a logic 0 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by th e target mcu. the host initiates the bit time but the target hcs08 finishes it. because the target wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 bdc clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 17-5. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 316 freescale semiconductor 17.2.3 bdc commands bdc commands are sent se rially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-first using a cust om bdc communicat ions protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 17-1 shows all hcs08 bdc commands, a shorthand de scription of their codi ng structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 17-1 to describe the coding stru cture of the bdc commands. commands begin with an 8-bit hexadeci mal command code in the host-to-target direction (most signi ficant bit first) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in th e target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target -to-host direction (fro m bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-tar get direction (for bdcb kpt breakpoint register)
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 317 table 17-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss r ead bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd r ead a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/ rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusiv e c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. re port status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 318 freescale semiconductor the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to us e for bdc communications until afte r it has analyzed the response to the sync command. to issue a sync command, the host: ? drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscill ator/64 or the self-clocked rate/64.) ? drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) ? removes all drive to the bkgd pin so it reverts to high impedance ? monitors the bkgd pin for the sync response pulse the target, upon detectin g the sync request fr om the host (which is a much longer low time than would ever occur during norma l bdc communications): ? waits for bkgd to re turn to a logic high ? delays 16 cycles to allow the host to stop driving the high speedup pulse ? drives bkgd low for 128 bdc clock cycles ? drives a 1-cycle high speedup pulse to force a fast rise time on bkgd ? removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync res ponse pulse and determines the correct speed for subsequent bdc communications. typically, the hos t can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware br eakpoint that compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this brea kpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the first instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten ) control bit in the bdc status and control re gister (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is di sabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg ) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the bdc module.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 319 17.3 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have be en built onto the chip with the mcu. the debug system consists of an 8-stage fifo that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status regist ers that are accessible in the user?s memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug module?s functions are used during development, a nd user programs rarely access any of the control and status registers for the debug modul e. the one exception is that the debug system can provide the means to implement a fo rm of rom patching. this topic is discussed in greater detail in section 17.3.6, ?hardware breakpoints .? 17.3.1 comparators a and b two 16-bit comparators (a and b) ca n optionally be qualified with the r/w signal and an opcode tracking circuit. separate control bits a llow you to ignore r/w for each compar ator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opc ode at the specified address is actually executed as opposed to onl y being read from memory into th e instruction queue. the comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. comparators are disabled temp orarily during all bdc accesses. the a comparator is always associated with the 16- bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. because the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address pl us data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpu?s write data bus is used. otherwise, the cpu?s read data bus is used. the currently selected trigger mode determines what the debugger logi c does when a comparator detects a qualified match condition. a match can cause: ? generation of a breakpoint to the cpu ? storage of data bus values into the fifo ? starting to store change-of-flow addre sses into the fifo (begin type trace) ? stopping the storage of change-of-flow a ddresses into the fifo (end type trace) 17.3.2 bus capture informat ion and fifo operation the usual way to use the fifo is to setup the trigger mode and other cont rol options, then arm the debugger. when the fifo has filled or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo . status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the inform ation is shifted by one position and
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 320 freescale semiconductor the host must perform ((8 ? cnt) ? 1) dummy reads of the fifo to advance it to the first significant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-flow addresses. in these cases, read dbgfh then dbgfl to get one coherent word of info rmation out of th e fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see section 17.3.5, ?trigger modes ? ), 8-bit data information is stored in to the fifo. in these cases, the high- order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. ea ch time dbgfl is read, the fifo is shifted so the next data value is av ailable through the fifo data port at dbgfl. in trigger modes where the fifo is storing change -of-flow addresses, there is a delay between cpu addresses and the input side of th e fifo. because of this delay, if the trigger event itself is a change-of-flow address or a change-o f-flow address appears during the ne xt two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. the fifo can also be used to generate a profile of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the addr ess of the most-recently fetched opcode to be saved in the fifo. to use the prof iling feature, a host debugger would re ad addresses out of the fifo by reading dbgfh then dbgfl at regul ar periodic intervals. the first eight values would be discarded because they correspond to the eight dbgfl reads needed to initially fill the fifo. additional periodic reads of dbgfh and dbgfl return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 17.3.3 change-of-flow information to minimize the amount of informati on stored in the fifo, only informat ion related to in structions that cause a change to the normal sequential execution of in structions is stored. w ith knowledge of the source and object code program stor ed in the target system, an external debugger system can reconstruct the path of execution through many instruct ions from the change -of-flow information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the a ddress of the conditional br anch opcode). because bra and brn instructions are not conditional, these events do not cause change-o f-flow information to be stored in the fifo. indirect jmp and jsr instruct ions use the current contents of the h: x index register pair to determine the destination address, so the debug system stores the r un-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-flow information. 17.3.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruc tion opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because any change-of-flow from a jump, bran ch, subroutine call, or interrupt causes some instructions that have been fetched into the in struction queue to be thrown away without being executed.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 321 a force-type breakpoint wa its for the current instruction to fi nish and then acts upon the breakpoint request. the usual action in respons e to a breakpoint is to go to ac tive background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminolo gy is used in two contexts within the debug module. the first context refers to breakpoint requests from the debug module to the cp u. the second refers to match signals from the comparators to the debugger control logi c. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opc ode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executi ng the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is se parate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 17.3.5 trigger modes the trigger mode controls the overa ll behavior of a debug run. the 4-bi t trg field in th e dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt regi ster, the output of the comparator must propagate through an opcode tracking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fi fo begins storing data wh en the qualified trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed unt il the qualified trigger is detected (end trigger). a debug run is started by wr iting a 1 to the arm bit in the dbgc register, which sets the armf flag and clears the af and bf flags and the cnt bits in dbgs. a be gin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to arm or dbgen in dbgc. in all trigger modes except event- only modes, the fifo stores change-of-flow addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only tri gger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not n ecessary to use r/w in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. it would also be unusual to specify trgsel = 1 while using a full m ode trigger because the opcode value is normally known at a particular address. the following trigger mode descripti ons only state the primary comparator conditions that lead to a trigger. either comparator can usually be further quali fied with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the si gnal from the comparator with optional r/w qualification is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 322 freescale semiconductor a-only ? trigger when the address matc hes the value in comparator a a or b ? trigger when the address matches either the value in comparator a or the value in comparator b a then b ? trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any num ber of cycles after the a match and before the b match. a and b data (full mode) ? this is called a full mode because address, data, a nd r/w (optionally) must match within the same bus cycle to cause a tri gger event. comparator a ch ecks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. a and not b data (full mode) ? address must match comparator a, data must not match the low half of comparator b, and r/w mu st match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. event-only b (store data) ? trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) ? after the address has matched the value in comparator a, a trigger event occurs each time the address ma tches the value in comparator b. tr igger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) ? a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ? a trigger occurs when the a ddress is either less than the value in comparator a or greater than the value in comparator b.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 323 17.3.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in section 17.3.5, ?trigger modes ,? to be used to gene rate a hardware breakpoint request to the cpu. tag in dbgc controls whether the breakpoint reque st will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it ente rs the instruction queue. if a tagged opcode reaches the end of the pipe, th e cpu executes a bgnd in struction to go to active background mode rather than execut ing the tagged opcode. a force-type breakpoint causes the cpu to finish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 17.4 register definition this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all dbg regist ers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to tr anslate these names into the appropriate absolute addresses. 17.4.1 bdc registers and control bits the bdc has two registers: ? the bdc status and control regist er (bdcscr) is an 8-bit regist er containing cont rol and status bits for the background debug controller. ? the bdc breakpoint match register (bdcbkpt ) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have a ddresses and cannot be a ccessed by user programs). some of the bits in the bdcscr ha ve write limitations; otherwise, thes e registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents th e ambiguous condition of the contro l bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be wr itten by the write_control serial bdc command. the clock switch (clksw) control bit may be r ead or written at any time.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 324 freescale semiconductor 17.4.1.1 bdc status and c ontrol register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 17-6. bdc status and control register (bdcscr) table 17-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ? typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the deb ug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ? this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ? if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ? when fts = 1, a breakpoint is request ed whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagg ed. if this tagged opcode ever reache s the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ? clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 325 17.4.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hard ware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and configure the breakpoint logi c. dedicated serial bdc commands (read_bkpt and write_bk pt) are used to read and writ e the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 17.2.4, ?bdc hardware breakpoint .? 17.4.2 system background debug force reset register (sbdfr) this register contains a single write-only contro l bit. a serial background mode command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. 2 ws wait or stop status ? when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force t he target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a backgro und command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status ? this status bit is set if a memory a ccess command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically , the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not conflict with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status ? this status bit is not used in the mc9s08el32 series and mc9s08sl16 series because it does not have any slow access memory. 0 memory access did not conflict with a slow memory access 1 memory access command failed because cpu was not finished with a slow memory access table 17-2. bdcscr register field descriptions (continued) field description
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 326 freescale semiconductor figure 17-7. system background debug force reset register (sbdfr) 17.4.3 dbg registers and control bits the debug module includes nine bytes of register spac e for three 16-bit register s and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal applic ation programs. these re gisters are rarely if ever accessed by normal user application programs with the possible ex ception of a rom patching mechanism that uses the breakpoint logic. 17.4.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high- order eight bits of comparat or a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low- order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high- order eight bits of comparat or b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low- order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. r e s e t00000000 = unimplemented or reserved table 17-3. sbdfr register field description field description 0 bdfr background debug force reset ? a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forc es an mcu reset. this bit cannot be written from a user program.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 327 17.4.3.5 debug fifo high register (dbgfh) this register provides read- only access to the high-order ei ght bits of the fifo. writes to this register have no meaning or effect. in the event- only trigger modes, the fifo only st ores data into the low-order byte of each fifo word, so this regist er is not used and will read 0x00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. 17.4.3.6 debug fifo low register (dbgfl) this register provides read- only access to the low-order ei ght bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the ne xt available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into th e fifo (high-order half of each fifo word is unused). when readi ng 8-bit words out of the fifo, simp ly read dbgfl repeatedly to get successive bytes of data from the fifo. it is n?t necessary to read dbgfh in this case. do not attempt to read data from th e fifo while it is still armed (after arming but before th e fifo is filled or armf is cleared) because the fifo is prevented from advancing during reads of dbgfl. this can interfere with normal sequenci ng of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodical ly, external host software can develop a prof ile of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the first read. to use the profiling feature, read the fifo eight times without using the data to prime the sequence and then begi n using the data to get a delayed picture of what addresses were be ing executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode.
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 328 freescale semiconductor 17.4.3.7 debug control register (dbgc) this register can be read or written at any time. 76543210 r dbgen arm tag brken rwa rwaen rwb rwben w reset00000000 figure 17-8. debug control register (dbgc) table 17-4. dbgc register field descriptions field description 7 dbgen debug module enable ? used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 0dbg disabled 1 dbg enabled 6 arm arm control ? controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and armf) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 0 debugger not armed 1 debugger armed 5 tag tag/force select ? controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 0 cpu breaks requested as force type requests 1 cpu breaks requested as tag type requests 4 brken break enable ? controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparat or(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fi fo becomes full. trgsel does not affect the timing of cpu break requests. 0 cpu break requests not enabled 1 triggers cause a break request to the cpu 3 rwa r/w comparison value for comparator a ? when rwaen = 1, this bit determines whether a read or a write access qualifies comparator a. when rwaen = 0, rw a and the r/w signal do not affect comparator a. 0 comparator a can only match on a write cycle 1 comparator a can only match on a read cycle 2 rwaen enable r/w for comparator a ? controls whether the level of r/w is considered for a comparator a match. 0 r/w is not used in comparison a 1 r/w is used in comparison a 1 rwb r/w comparison value for comparator b ? when rwben = 1, this bit determines whether a read or a write access qualifies comparator b. when rwben = 0, rw b and the r/w signal do not affect comparator b. 0 comparator b can match only on a write cycle 1 comparator b can match only on a read cycle 0 rwben enable r/w for comparator b ? controls whether the level of r/w is considered for a comparator b match. 0 r/w is not used in comparison b 1 r/w is used in comparison b
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 329 17.4.3.8 debug trigger register (dbgt) this register can be read any time , but may be written only if arm = 0, except bits 4 and 5 are hard-wired to 0s. 76543210 r trgsel begin 00 trg3 trg2 trg1 trg0 w r e s e t00000000 = unimplemented or reserved figure 17-9. debug trigger register (dbgt) table 17-5. dbgt regist er field descriptions field description 7 trgsel trigger type ? controls whether the match outputs from com parators a and b are qualified with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparat or a or b must propagate through the opcode tracking logic and a trigger event is on ly signalled to the fifo logi c if the opcode at the match address is actually executed. 0 trigger on access to compare address (force) 1 trigger if opcode at compare address is executed (tag) 6 begin begin/end trigger select ? controls whether the fifo starts filling at a trigger or fills in a circular manner until a trigger ends the capture of informati on. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 data stored in fifo until trigger (end trace) 1 trigger initiates data storage (begin trace) 3:0 trg[3:0] select trigger mode ? selects one of nine triggering modes, as described below. 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ? 1111 (no trigger)
development support mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 330 freescale semiconductor 17.4.3.9 debug status register (dbgs) this is a read-onl y status register. 76543210 r af bf armf 0 cnt3 cnt2 cnt1 cnt0 w r e s e t00000000 = unimplemented or reserved figure 17-10. debug status register (dbgs) table 17-6. dbgs register field descriptions field description 7 af trigger match a flag ? af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 0 comparator a has not matched 1 comparator a match 6 bf trigger match b flag ? bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 0 comparator b has not matched 1 comparator b match 5 armf arm flag ? while dbgen = 1, this status bit is a read-only im age of arm in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trac e) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to arm or dbgen in dbgc. 0 debugger not armed 1 debugger armed 3:0 cnt[3:0] fifo valid count ? these bits are cleared at the start of a debu g run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping trac k of the count as information is read out of the fifo. 0000 number of valid words in fifo = no valid data 0001 number of valid words in fifo = 1 0010 number of valid words in fifo = 2 0011 number of valid words in fifo = 3 0100 number of valid words in fifo = 4 0101 number of valid words in fifo = 5 0110 number of valid words in fifo = 6 0111 number of valid words in fifo = 7 1000 number of valid words in fifo = 8
mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 331 appendix a electrical characteristics a.1 introduction this section contains the most accurate electrical and timing information for the mc9s08el32 series and mc9s08sl16 series of microcontrollers available at the time of publication. a.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. a.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table a-2 may affect device reliability or cause permanent damage to the de vice. for functional operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table a-1. paramete r classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 332 freescale semiconductor a.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the mcu design. to take p i/o into account in power calc ulations, determine the diff erence between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the diff erence between pin voltage and v ss or v dd is very small. table a-2. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load shunts current greater than maximum injection current. this is the greatest risk when the mcu is not consuming power. for example, if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?55 to 150 c table a-3. thermal characteristics num c rating symbol value unit 1? operating temperature range (packaged) temperature code m t a ?40 to 125 c temperature code v ?40 to 105 temperature code c ?40 to 85 2d thermal resistance 1,2 single-layer board 20-pin tssop ja 113 c/w 28-pin tssop 91 3d thermal resistance 1,2 four-layer board 20-pin tssop ja 73 c/w 28-pin tssop 58 4 d maximum junction temperature t j 135 c
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 333 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. a-2 solving equation a-1 and equation a-2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation a-1 and equation a-2 iteratively for any value of t a . a.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. all esd testing is in conformity with aec-q100 stress test qual ification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm) and the char ge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is perf ormed per the applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification. 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 junction to ambient natural convection
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 334 freescale semiconductor a.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table a-4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 3 latch-up minimum input voltage limit ? 2.5 v maximum input voltage limit 7.5 v table a-5. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 charge device model (cdm) v cdm 500 ? v 3 latch-up current at t a = 125 ci lat 100 ? ma table a-6. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 ? operating voltage v dd 2.7 5.5 v 2 c all i/o pins, 5 v, i load = ?4 ma v dd ? 1.5 ? ? p low-drive strength 5 v, i load = ?2 ma v dd ? 0.8 ? ? c output high v oh 3 v, i load = ?1 ma v dd ? 0.8 ? ? v c voltage 5 v, i load = ?20 ma v dd ? 1.5 ? ? p all i/o pins, 5 v, i load = ?10 ma v dd ? 0.8 ? ? c high-drive strength 3 v, i load = ?5 ma v dd ? 0.8 ? ? 3d output high current max total i oh for all ports i oht v out < v dd 0 ? ?100 ma 4 c all i/o pins 5 v, i load = 4 ma ? ? 1.5 p low-drive strength 5 v, i load = 2 ma ? ? 0.8 c output low v ol 3 v, i load = 1 ma ? ? 0.8 v c voltage 5 v, i load = 20 ma ? ? 1.5 p alli/o pins 5 v, i load = 10 ma ? ? 0.8 c high-drive strength 3 v, i load = 5 ma ? ? 0.8 5d output low current max total i ol for all ports i olt v out > v ss 0?100ma 6 p input high voltage; all digital inputs v ih 5v 0.65 x v dd ??v c 3v 0.7 x v dd ??
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 335 7 p input low voltage; all digital inputs v il 5v ? ? 0.35 x v dd v c 3v ? ? 0.35 x v dd c input hysteresis v hys 0.06 x v dd v 8 9 p input leakage current (per pin) | i in | v in = v dd or v ss ?? 1 a 10 hi-z (off-state) leakage current (per pin) p input/output port pins | i oz | v in = v dd or v ss ?? 1 a ptb6/sda/xtal, reset v in = v dd or v ss ?? 2 a 11 pullup or pulldown 2 resistors; when enabled p i/o pins r pu ,r pd 17 37 52 k c reset 3 r pu 17 37 52 k 12 dc injection current 4, 5, 6, 7 single pin limit v in > v dd 0?2ma di ic v in < v ss , 0 ? ?0.2 ma total mcu limit, includes v in > v dd 0?25ma sum of all stressed pins v in < v ss , 0 ? ?5 ma 13 d input capacitance, all pins c in ?? 8pf 14 d ram retention voltage v ram ?0.61.0v 15 d por re-arm voltage 8 v por 0.9 1.4 2.0 v 16 d por re-arm time 9 t por 10 ? ? s 17 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d 1 3.9 4.0 4.0 4.1 4.1 4.2 v 18 p low-voltage detection threshold ? low range v dd falling v dd rising v lv d 0 2.48 2.54 2.56 2.62 2.64 2.70 v 19 p low-voltage warning threshold ? high range 1 v dd falling v dd rising v lv w 3 4.5 4.6 4.6 4.7 4.7 4.8 v 20 p low-voltage warning threshold ? high range 0 v dd falling v dd rising v lv w 2 4.2 4.3 4.3 4.4 4.4 4.5 v 21 p low-voltage warning threshold low range 1 v dd falling v dd rising v lv w 1 2.84 2.90 2.92 2.98 3.00 3.06 v 22 p low-voltage warning threshold ? low range 0 v dd falling v dd rising v lv w 0 2.66 2.72 2.74 2.80 2.82 2.88 v table a-6. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 336 freescale semiconductor figure a-1. typical v ol vs i ol , high drive strength 23 t low-voltage inhibit reset/recover hysteresis v hys 5 v ? 100 ? mv 3 v ? 60 ? 24 p bandgap voltage reference 10 v bg 1.18 1.202 1.21 v 1 typical values are measured at 25 c. characterized, not tested 2 when a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors. 3 the specified resistor value is the actual value internal to the device. the pullup value may measure higher when measured externally on the pin. 4 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load shunts current greater than maximum injection current. this is the greatest risk when the m cu is not consuming power. for example, if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 5 all functional non-su pply pins except reset are internally clamped to v ss and v dd . 6 input must be current limited to the value specified. to determine the value of the required current-limitin g resistor, calcula te resistance values for positive and negative clamp volt ages, then use the larger of the two values. 7 the reset pin does not have a clamp diode to v dd . do not drive this pin above v dd . 8 maximum is highest voltage that por is guaranteed. 9 simulated, not tested. 10 factory trimmed at v dd = 5.0 v, temp = 25 c. table a-6. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit v ol (v) i ol (ma) 20 15 10 5 025 0 0.5 1 1.5 2 a) v dd = 5v, high drive v ol (v) i ol (ma) 8642 01 0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, high drive 0.6 125c 25c ?40c max 0.8v@5ma max 1.5v@25ma 125c 25c ?40c
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 337 figure a-2. typical v ol vs i ol , low drive strength figure a-3. typical v dd ? v oh vs i oh , high drive strength v ol (v) i ol (ma) 4321 05 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, low drive v ol (v) i ol (ma) 1.6 1.2 0.8 0.4 02.0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, low drive 0.6 125c 25c ?40c max 0.8v@1ma max 1.5v@4ma i oh (ma) ?20 ?15 ?10 ?5 0? 2 5 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, high drive i oh (ma) ?8 ?6 ?4 ?2 0?10 0 0.2 0.4 0.8 1.0 b) v dd = 3v, high drive 0.6 125c 25c ?40c max 0.8v@5ma max 1.5v@20ma v dd ? v oh (v) v dd ? v oh (v)
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 338 freescale semiconductor figure a-4. typical v dd ? v oh vs i oh , low drive strength a.7 supply current characteristics this section includes information about power supply current in various operating modes. table a-7. supply current characteristics num c parameter symbol v dd (v) typ 1 max 2 unit 1 c run supply current 3 measured at (cpu clock = 4 mhz, f bus = 2 mhz) ri dd 51.7 2.5 ma c 31.7 2.4 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 55.1 8.5ma c3 5 . 0 8 . 4 3 c run supply current 4 measured at (cpu clock = 32 mhz, f bus = 16mhz) ri dd 57.8 15 ma c 37.7 14 4 stop3 mode supply current c? 4 0 c (c, v, & m suffix) 1.0 ? p2 5 c (all parts) 1.0 ? p 5 85 c (c suffix only) 5 6.8 40.0 a p 5 105 c (v suffix only) 15.6 50.0 p 5 125 c (m suffix only) s3i dd 42 75.0 c ?40 c (c,v, & m suffix) 0.9 ? p2 5 c (all parts) 0.9 ? p 5 85 c (c suffix only) 3 6.0 35.0 a p 5 105 c (v suffix only) 13.1 45.0 p 5 125 c (m suffix only) 38 70.0 v dd ? v oh (v) i oh (ma) ?4 ?3 ?2 ?1 0?5 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, low drive i oh (ma) ?1.6 ?1.2 ?0.8 ?0.4 0? 2 . 0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, low drive 0.6 125c 25c ?40c max 0.8v@1ma max 1.5v@4ma v dd ? v oh (v)
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 339 5 stop2 mode supply current c? 4 0 c (c,m, & v suffix) 0.9 ? p2 5 c (all parts) 0.9 ? p 5 85 c (c suffix only) 5 5.0 40.0 a p 5 105 c (v suffix only) 11.0 50.0 p 5 125 c (m suffix only) s2i dd 29.1 65.0 c? 4 0 c (c,m, & v suffix) 0.9 ? p2 5 c (all parts) 0.9 ? p 5 85 c (c suffix only) 3 4.2 35.0 a p 5 105 c (v suffix only) 8.8 45.0 p 5 125 c (m suffix only) 25 60.0 6 c rtc adder to stop2 or stop3 6 s23i ddrti 5300500na 3300500na 7 c lvd adder to stop3 (lvde = lvdse = 1) s3i ddlvd 5110180 a 390160 a 8 c adder to stop3 for oscillator enabled 7 (erefsten =1) s3i ddosc 5,3 5 8 a 1 typical values for specs 1, 2, 3, 6, 7, and 8 are based on characterization data at 25 c. see figure a-5 through figure a-7 for typical curves across temperature and voltage. 2 max values in this column apply for the full operat ing temperature range of th e device unless otherwise noted. 3 all modules except adc active, ics configured for fbelp, and does not include any dc loads on port pins 4 all modules except adc active, ics configured for fei, and does not include any dc loads on port pins 5 stop currents are tested in production for 25 c on all parts. tests at other temperatures depend upon the part number suffix and maturity of the product. freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficient data has been collectd and is approved. 6 most customers are expected to find that auto-wakeup from stop2 or stop3 ca n be used instead of the higher current wait mode. 7 values given under the following conditions: low ra nge operation (range = 0) with a 32.768khz crystal and low power mode (hgo = 0). table a-7. supply current characteristics (continued) num c parameter symbol v dd (v) typ 1 max 2 unit
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 340 freescale semiconductor figure a-5. typical run i dd vs. bus frequency (v dd = 5v) figure a-6. typical run and wait i dd vs. temperature (v dd = 5v; f bus = 8mhz) run i dd (ma) f bus (mhz) 8 421 01 6 0 2 4 10 20 6 8 fei fbelp 12 run i dd ( a) temperature ( c ) 85 25 0 ?40 105 0 1 2 5 125 3 4 run wait 6
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 341 figure a-7. typical stop i dd vs. temperature (v dd = 5v) a.8 external oscillator (xosc) characteristics table a-8. oscillator electrical specifications (temperature range = ?40 to 125 c ambient) num c rating symbol min typ 1 max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) f lo 32 ? 38.4 khz high range (range = 1) fee or fbe mode 2 f hi 1?5mhz high range (range = 1, hgo = 1) fbelp mode f hi-hgo 1?16mhz high range (range = 1, hgo = 0) fbelp mode f hi-lp 1?8mhz 2? load capacitors c 1, c 2 see crystal or resonator manufacturer?s recommendation. 3? feedback resistor r f m low range (32 khz to 100 khz) ? 10 ? high range (1 mhz to 16 mhz) ? 1 ? 4? series resistor r s k low range, low gain (range = 0, hgo = 0) ? 0 ? low range, high gain (range = 0, hgo = 1) ? 100 ? high range, low gain (range = 1, hgo = 0) ? 0 ? high range, high gain (range = 1, hgo = 1) 8 mhz ? 0 0 4 mhz ? 0 10 1 mhz ? 0 20 stop i dd ( a) temperature ( c ) 85 25 0 ?40 105 0 10 20 50 125 30 40 60 stop2 stop3
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 342 freescale semiconductor a.9 internal clock source (ics) characteristics 5t crystal start-up time 3 ms low range, low gain (range = 0, hgo = 0) t cstl-lp ? 200 ? low range, high gain (range = 0, hgo = 1) t cstl-hgo ? 400 ? high range, low gain (range = 1, hgo = 0) 4 t csth-lp ?5? high range, high gain (range = 1, hgo = 1) 4 t csth-hgo ?20? 6t square wave input clock frequency (erefs = 0, erclken = 1) f extal fee or fbe mode 2 0.03125 ? 5 mhz fbelp mode 0 ? 40 mhz 1 typical data was characterized at 5.0 v, 25 c or is recommended value. 2 the input clock source must be divided using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 characterized and not tested on each device. proper pc board layout procedures must be followed to achieve specifications. 4 4 mhz crystal table a-9. ics frequency specifications (temperature range = ?40 to 125 c ambient) num c rating symbol mi n typical max unit 1p internal reference frequency ? factory trimmed at v dd = 5 v and temperature = 25 c f int_ft ? 31.25 ? khz 2t internal reference frequency ? untrimmed 1 f int_ut 25 36 41.66 khz 3 p internal reference frequency ? trimmed f int_t 31.25 ? 39.0625 khz 4 d internal reference startup time t irefst ?55100 s 5? dco output frequency range ? untrimmed 1 value provided for reference: f dco_ut = 1024 x f int_ut f dco_ut 25.6 36.86 42.66 mhz 6 d dco output frequency range ? trimmed f dco_t 32 ? 40 mhz 7d resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 8d resolution of trimmed dco output frequency at fixed voltage and temperatur e (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco table a-8. oscillator electrical specifications (temperature range = ?40 to 125 c ambient) (continued) num c rating symbol min typ 1 max unit mcu extal xtal crystal or resonator r s c 2 r f c 1
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 343 figure a-8. typical frequency deviation vs temperature (ics trimmed to 16mhz bus@25c, 5v, fei) 1 a.10 analog comparator (acmp) electricals 9d total deviation of trimmed dco output frequency over voltage and temperature f dco_t ? + 0.5 ? 1.0 2 %f dco 10 d total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 c to 70 c f dco_t ? 0.5 1 %f dco 11 d fll acquisition time 2 t acquire 1ms 12 d dco output clock long term jitter (over 2 ms interval) 3 c jitter ?0.020.2 %f dco 1 trim register at default value (0x80) and ftrim control bit at default value (0x0). 2 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll en abled (fei, fee, fbe, fbi). if a crystal/re sonator is being used as the reference, this specification assumes it is already running. 3 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injecte d into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 1. based on the average of several hundred units from a typical characterization lot. table a-10. analog comparator electrical specifications num c rating symbol min typical max unit 1 ? supply voltage v dd 2.7 ? 5.5 v 2 c/t supply current (active) i ddac ?2035 a 3 d analog input voltage v ain v ss ? 0.3 ? v dd v table a-9. ics frequency specifications (continued) (temperature range = ?40 to 125 c ambient) num c rating symbol mi n typical max unit deviation from trimmed frequency temperature ( c ) 85 25 0 ?40 105 ?2% ?1% +2% 125 +1% 0
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 344 freescale semiconductor a.11 adc characteristics 4 d analog input offset voltage v aio 20 40 mv 5d analog comparator hysteresis v h 3.0 6.0 20.0 mv 6 d analog input leakage current i alkg ??1 .0 a 7 d analog comparator initialization delay t ainit ??1 .0 s table a-11. adc operating conditions num characteristic conditions symb min typ 1 1 typical values assume v ddad = v dd = 5.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment 1 supply voltage absolute v ddad 2.7 ? 5.5 v 2 input voltage v adin v refl ?v refh v 3 input capacitance c adin ?4.55.5pf 4 input resistance r adin ?3 5k 5 analog source resistance 10 bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 5 10 k external to mcu 6 8 bit mode (all valid f adck )? ? 1 0 7 adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz 8 low power (adlpc=1) 0.4 ? 4.0 table a-10. analog comparator electrical specifications (continued) num c rating symbol min typical max unit
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 345 figure a-9. adc input impedance equivalency diagram table a-12. adc characteristics characteristic condi tions c symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 ti dd + i ddad ?133? a adc current only adlpc=1 adlsmp=0 adco=1 ti dd + i ddad ?218? a adc current only adlpc=0 adlsmp=1 adco=1 ti dd + i ddad ?327? a adc current only adlpc=0 adlsmp=0 adco=1 pi dd + i ddad ? 0.582 1 ma adc current only adc asynchronous clock source high speed (adlpc=0) p f adack 23.35mhzt adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 346 freescale semiconductor conversion time (including sample time) short sample (adlsmp=0) d t adc ?20?adck cycles see adc chapter for conversion time variances long sample (adlsmp=1) ? 40 ? sample time short sample (adlsmp=0) d t ads ?3.5?adck cycles long sample (adlsmp=1) ? 23.5 ? total unadjusted error (includes quantization) 28-pin packages only 10 bit mode p e tue ? 1 2.5 lsb 2 8 bit mode ? 0.5 1 20-pin packages only 10 bit mode p e tue ? .5 3.5 lsb 2 8 bit mode ? 0.7 1.5 differential non-linearity 10-bit mode p dnl ? 0.5 1.0 lsb 2 8-bit mode ? 0.3 0.5 monotonicity and no-missing-codes guaranteed integral non-linearity 10-bit mode t inl ? 0.5 1.0 lsb 2 8-bit mode ? 0.3 0.5 zero-scale error 28-pin packages only 10-bit mode p e zs ? 0.5 1.5 lsb 2 8-bit mode ? 0.5 0.5 20-pin packages only 10-bit mode p e zs ? 1.5 2.5 lsb 2 8-bit mode ? 0.5 0.7 full-scale error 28-pin packages only 10-bit mode t e fs 0 0.5 1lsb 2 8-bit mode 0 0.5 0.5 20-pin packages only 10-bit mode t e fs 0 1.0 1.5 lsb 2 8-bit mode 0 0.5 0.5 quantization error 10-bit mode d e q ?? 0.5 lsb 2 8-bit mode ? ? 0.5 input leakage error 10-bit mode d e il 0 0.2 2.5 lsb 2 pad leakage 3 * r as 8-bit mode 0 0.1 1 table a-12. adc characteristics (continued) characteristic condi tions c symb min typ 1 max unit comment
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 347 a.12 ac characteristics this section describes ac timing charac teristics for each peripheral system. a.12.1 control timing temp sensor slope -40 c to 25 c d m ? 3.266 ? mv/ c 25c to 125 c ? 3.638 ? temp sensor voltage 25cd v temp25 ? 1.396 ? v 1 typical values assume v dd = 5.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typi cal values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 based on input pad leakage current. refer to pad electricals. table a-13. control timing num c rating symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus )f bus dc ? 20 mhz 2 d internal low power oscillator period t lpo 800 1500 s 3d external reset pulse width 2 2 this is the shortest pulse that is guarant eed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 100 ? ns 4d reset low drive 3 3 when any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t cyc . after por reset, the bus clock frequency changes to the untrimmed dco frequency (f reset = (f dco_ut )/4) because trim is reset to 0x80 and ftrim is reset to 0, and there is an extra divide-by-two because bdiv is rese t to 0:1. after other resets trim stays at the pre-reset value. t rstdrv 66 x t cyc ?ns 5d pin interrupt pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. t ilih, t ihil 100 1.5 x t cyc ??ns 6 c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 125 c. t rise , t fall ? ? 40 75 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 11 35 ? ? ns table a-12. adc characteristics (continued) characteristic condi tions c symb min typ 1 max unit comment
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 348 freescale semiconductor figure a-10. reset timing figure a-11. pin interrupt timing a.12.2 tpm/mtim module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure a-12. timer external clock table a-14. tpm input timing num c rating symbol min max unit 1? external clock frequency (1/t tclk )f tclk dc f bus /4 mhz 2 ? external clock period t tclk 4? t cyc 3 ? external clock high time t clkh 1.5 ? t cyc 4 ? external clock low time t clkl 1.5 ? t cyc 5 ? input capture pulse width t icpw 1.5 ? t cyc t extrst reset pin t ihil pin interrupts t ilih pin interrupts t tclk t clkh t clkl tclk
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 349 figure a-13. timer input capture pulse a.12.3 spi table a-15 and figure a-14 through figure a-17 describe the timing require ments for the spi system. table a-15. spi electrical characteristic num 1 cr a t i n g 2 symbol min max unit 1 d cycle time master slave t sck t sck 2 4 2048 ? t cyc t cyc 2 d enable lead time master slave t lead t lead ? 1/2 1/2 ? t sck t sck 3 d enable lag time master slave t lag t lag ? 1/2 1/2 ? t sck t sck 4 d clock (spsck) high time master and slave t sckh 1/2 t sck ? 25 ? ns 5 d clock (spsck) low time master and slave t sckl 1/2 t sck ? 25 ? ns 6 d data setup time (inputs) master slave t si(m) t si(s) 30 30 ? ? ns ns 7 d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ? ? ns ns 8 d access time, slave 3 t a 04 0n s 9 d disable time, slave 4 t dis ?4 0n s 10 d data setup time (outputs) master slave t so t so ? ? 25 25 ns ns t icpw tpmchn t icpw tpmchn
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 350 freescale semiconductor figure a-14. spi master timing (cpha = 0) 11 d data hold time (outputs) master slave t ho t ho ?10 ?10 ? ? ns ns 12 d operating frequency master slave f op f op f bus /2048 dc 5 5 f bus /4 mhz 1 refer to figure a-14 through figure a-17 . 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. 3 time to data active from high-impedance state. 4 hold time to high-impedance state. 5 maximum baud rate must be limited to 5 mhz due to input filter characteristics. table a-15. spi electrical characteristic (continued) num 1 cr a t i n g 2 symbol min max unit sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 351 figure a-15. spi master timing (cpha = 1) figure a-16. spi slave timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4 sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 11 5 5 4
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 352 freescale semiconductor figure a-17. spi slave timing (cpha = 1) a.13 flash and eeprom specifications this section provides details about program/erase ti mes and program-erase endurance for the flash and eeprom memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information about progra m/erase operations, see the memory section. table a-16. flash characteristics num c characteristic symbol min typical max unit 1 ? supply voltage for program/erase v prog/erase 2.7 5.5 v 2 ? supply voltage for read operation v read 2.7 5.5 v 3 ? internal fclk frequency 1 f fclk 150 200 khz 4 ? internal fclk period (1/f fclk )t fcyc 56 . 6 7 s 5 ? byte program time (random location) 2 t prog 9t fcyc 6 ? byte program time (burst mode) 2 t burst 4t fcyc 7 ? page erase time 2 t page 4000 t fcyc 8 ? mass erase time 2 t mass 20,000 t fcyc 9c program/erase endurance 3 t l to t h = ?40 c to +125 c t = 25 c n flpe 10,000 ? 100,000 ? ? cycles sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 11 4 5 5
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 353 a.14 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and char acteristics of external components as well as mcu software operation all pl ay a significant role in emc performance. the system designer should consult freescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifi cally targeted at optimizing emc performance. a.14.1 radiated emissions microcontroller radiated rf emis sions are measured from 150 khz to 1 ghz using th e tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installe d on a custom emc evalua tion board while running specialized emc test software. the radiated emissions fr om the microcontroller are measured in a tem cell in two package orientations (north and east). the maximum radiated rf emissions of the tested configuration in all or ientations are less than or equal to the reported emissions levels. 10 c eeprom program/erase endurance 3 t l to t h = ?40 c to + 0 c t l to t h = 0 c to + 125 c t = 25 c n eepe 10,000 50,000 100,000 ? ? ? cycles 11 c data retention 4 t d_ret 15 100 ? years 1 the frequency of this clock is controlled by a software setting. 2 these values are hardware state machine co ntrolled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. 3 typical endurance for flash is based upon the intrinsic bit cell performance. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 4 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional informat ion on how freescale semiconductor defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. table a-17. radiated emissions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) unit radiated emissions, electric field v re_tem v dd = 5.0v t a = +25 o c package type 28 tssop 0.15 ? 50 mhz 4mhz crystal 20mhz bus 11 db v 50 ? 150 mhz 12 150 ? 500 mhz 3 500 ? 1000 mhz ? 10 iec level n/a ? sae level 2 ? table a-16. flash characteristics (continued) num c characteristic symbol min typical max unit
appendix a electrical characteristics mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 354 freescale semiconductor a.14.2 conducted transient susceptibility microcontroller transient conducted su sceptibility is measured in accord ance with an internal freescale test method. the measurement is performed with the microcontroller inst alled on a custom emc evaluation board and running specialize d emc test software designed in compliance with the test method. the conducted susceptibility is determined by injecti ng the transient susceptibility signal on each pin of the microcontroller. the transient waveform and injection methodology is based on iec 61000-4-4 (eft/b). the transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reporte d levels unless otherwise i ndicated by footnotes below table a-18 . the susceptibility performance classification is described in table a-19 . 1 data based on qualification test results. table a-18. conducted susceptibility, eft/b parameter symbol conditions f osc /f bus result amplitude 1 (min) 1 data based on qualification test re sults. not tested in production. unit conducted susceptibility, electrical fast transient/burst (eft/b) v cs_eft v dd = 5.0v t a = +25 o c 28 tssop package type 4mhz crystal 20mhz bus an / a v b 300 ? 3700 cn / a dn / a e ? 3800 table a-19. susceptibility performance classification result performance criteria a no failure the mcu performs as designed during and after exposure. b self-recovering failure the mcu does not perform as designed during exposure. the mcu returns automatically to normal operation after exposure is removed. c soft failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is remo ved and the reset pin is asserted. d hard failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the power to the mcu is cycled. e damage the mcu does not perform as designed during and after exposure. the mcu cannot be returned to proper operation due to physical damage or other permanent performance degradation.
appendix b ordering information and mechanical drawings mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 freescale semiconductor 355 appendix b ordering information and mechanical drawings b.1 ordering information this section contains ordering information for mc9s08el32 series and mc9s08sl16 series devices. b.1.1 device numbering scheme this device uses a smart numbering system. refer to the following diagram to understand what each element of the device number represents. figure b-1. mc9s08el32 and mc9s08sl16 device numbering scheme table b-1. devices in the mc9s08el32 series and mc9s08sl16 series device number 1 1 see table 1-1 for a complete description of modules included on each device. memory available packages 2 2 see ta b l e b - 2 for package information. flash ram eeprom mc9s08el32 32,768 1024 512 28-tssop, 20-tssop mc9s08el16 16,384 mc9s08sl16 16,384 512 256 mc9s08sl8 8,192 s9s08el n e1 c xx r status - s = auto qualified main memory type - 9 = flash-based core family - el or sl memory size - 32 kbytes - 16 kbytes mask set identifier ? this field only appears in ?auto qualified? part numbers - alpha character references wafer fab. - numeric character identifies mask. temperature option - c = ?40 to 85 c - v = ?40 to 105 c - m = ?40 to 125 c package designator two letter descriptor (refer to ta b l e b - 2 ). tape and reel suffix (optional) - r = tape and reel
appendix b ordering information and mechanical drawings mc9s08el32 series and mc9s08sl16 series data sheet, rev. 3 356 freescale semiconductor b.2 mechanical drawings the latest package outline drawings ar e available on the product summary pages on http://www.freescale.com . table b-2 lists the document numbers per p ackage type. use these numbers in the web page?s keyword search engine to find the latest package outline drawings. table b-2. package descriptions pin count type abbreviation designator document no. 28 thin shrink small outline package tssop tl 98ars23923w 20 thin shrink small outline package tssop tj 98ash70169a

mc9s08el32 rev. 3, 7/2008 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 1-303-675-2140 fax: 1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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